• Editorial updates.
• Table 40 “PLL configuration examples” updated.
• Register bit description of Table 92 “Pattern match bit-slice source register (PMSRC, address 0xA000 402C) bit description” updated.
• Chapter 5 “LPC800 Reduced power modes and Power Management Unit (PMU)” updated.
• Section 5.3.1 “Low power modes in the ARM Cortex-M0+ core” added.
• Removed dependency on system frequency for flash access times in Table 213 “Flash configuration register (FLASHCFG, address 0x4004 0010) bit description”.
The LPC81xM are an ARM Cortex-M0+ based, low-cost 32-bit MCU family operating at
CPU frequencies of up to 30 MHz. The LPC81xM support up to 16 kB of flash memory
and 4 kB of SRAM.
The peripheral complement of the LPC81xM includes a CRC engine, one I2C-bus
interface, up to three USARTs, up to two SPI interfaces, one multi-rate timer, self wake-up
timer, and state-configurable timer, one comparator, function-configurable I/O ports
through a switch matrix, an input pattern match engine, and up to 18 general-purpose I/O
The Application Note describes the steps involved in writing a flash programming algorithm for unsupported Cortex -M devices. The algorithm will be used in conjunction with the LPCXpresso IDE to flash the binary files onto the Flash memory on the board. The accompanying project implements a Flash Programming algorithm for the MCB1800/4300.