user guide

LPC23XX User manual

emWin
Graphic Library with
Graphical User Interface
Version 5.16

Manual Rev. 0

1. Introduction

The NXP LPC314x combine a 270 MHz ARM926EJ-S CPU core, High-speed USB 2.0 OTG, 192 KB SRAM, NAND flash controller, flexible external bus interface, three channel 10-bit A/D, and a myriad of serial and parallel interfaces in a single chip targeted at consumer, industrial, medical, and communication markets. To optimize system power consumption, the LPC314x have multiple power domains and a very flexible Clock Generation Unit (CGU) that provides dynamic clock gating and scaling.

1. General description

The NXP LPC3152/3154 combine an 180 MHz ARM926EJ-S CPU core, High-speed USB
2.0 OTG, 192 kB SRAM, NAND flash controller, flexible external bus interface, an
integrated audio codec, Li-ion charger, Real-Time Clock (RTC), and a myriad of serial and
parallel interfaces in a single chip targeted at consumer, industrial, medical, and
communication markets. To optimize system power consumption, the LPC3152/3154
have multiple power domains and a very flexible Clock Generation Unit (CGU) that
provides dynamic clock gating and scaling.

LPC3130/31 User manual

LPC11Exx User manual

Rev 6 20130312 modifications:

• Added instructions on how to minimize power consumption due to floating nodes in Section 3.6 and Section 9.3.
• Added instructions on when to change flash access times. See Section 17.9.1.

Rev 4 Modifications:

• Table 379 “Flash configuration register (FLASHCFG, address 0x4003 C010) bit description” corrected.
• Description of the NMISRC register updated. See Section 3.5.29 “NMI Source Control register (NMISRC)”.

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The LPC122x extend NXP's 32-bit ARM microcontroller continuum and target a wide range of industrial applications in the areas of factory and home automation. Benefitting from the ARM Cortex-M0 Thumb instruction set, the LPC122x have up to 50 % higher code density compared to common 8/16-bit microcontroller performing typical tasks. The LPC122x also feature an optimized ROM-based divide library for Cortex-M0, which offers several times the arithmetic performance of software based libraries, as well as highly deterministic cycle time combined with reduced flash code size.