Introduction to Cortex Serial Wire Debugging, Part One

Part Two
Part Three

LPC ARM Cortex-based microcontrollers from NXP can be controlled via SWD, ARM’s Serial Wire Debug protocol and the Coresight register set which allow nonintrusive debugging. This blog post series summarizes use of the SWD protocol to do basic debugging functions on the Cortex-M0 and presents demonstration code and a simple hardware design to implement a USB-to-SWD bridge. With additional software the SWD-to-USB bridge could allow debugging or flash programming from a computer or other USB host device.

Serial Wire Debug (SWD) Fundamentals.

The SWD interface has two signal wires, SWCLK and SWDIO. SWCLK or Serial Wire Clock is driven by the master and synchronizes the SWD data transfer. SWDIO or Serial Wire Data Input/Output is driven by either the master or the target. Every SWD transaction starts with the master driving SWDIO but switches to having the target drive SWDIO at some point. I/O levels and thresholds on SWCLK and SWDIO should be set to match the I/O voltage of the target. In the simplistic hardware design given in this document, we assume that the target voltage is 3.3V and no provisions are made to adjust to lower target voltages.

SWD Levels and Edges.

Since SWD is a bi-directional communications standard with only one data line, data needs to be written to the bus by both the master and the slave. Every SWD transaction begins with the master controlling SWDIO. After a turnaround period, the slave controls SWDIO, then control switches back to the master. Whenever the bus is idle, the clock should be high and the master controls the bus. When the master is in control of SWDIO, it clocks data out on the falling edge of SWCLK and the slave latches the data on the rising edge of SWCLK. When the slave takes over SWDIO, it presents data to SWDIO on the rising edge of SWCLK and the master latches the incoming data on the falling edge of SWCLK. In both cases, SWCLK is driven by the master. The 1/2 and 1 1/2 period 1 values on SWDIO are called “turnaround periods” in the SWD specification. They need to be driven by the host to prevent the bus from being dragged low by coupling of transitions on the SWDCLK. If the SWD target detects that SWDIO is not 1 during the turnaround period, it will go into an error state and not respond to any further transactions.

SWD Protocol.

The swd protocol consists of read and write transactions. Both types of transactions have three phases. These phases are the request phase, the acknowledge phase, and the data phase. All of the data sent over SWD is sent in little-endian order and is sent least-significant-bit first. During the request phase the host requests a read or write operation on the target and indicates whether the Debug Port or Access Port is being accessed. The Debug Port is a set of four important registers within the Cortex debug port that perform very basic operations. The Access Port is a larger address space of 64 registers which are useful for accessing the microcontroller’s main bus. The request phase consists of eight bits of data, some of which are constant.
The acknowledge phase consists of three bits where the SWD target indicates status to the host. The data phase is where data is sent from the host to the target during a write operation. Data is sent from the target to the master during a read operation. The data phase consists of 33 bits- 32 bits of data (lsb first) followed by 1 bit of parity.

Request phase data

bit numberbit valuebit description
0 (lsb)always 1start bit
11 for Access PortSWD Port select- selects Access Port or Debug Port
21 for Readread select- selects whether this is a read or a write transaction
3address bit 2bit 2 of read or write address (bits 0 and 1 are 0)
4address bit 3bit 3 of read or write address (bits 0 and 1 are 0)
5parity1 if sum of request phase bits 1-4 is odd
6always 0stop bit
7 (msb)always 1park bit

Acknowledge phase data

bit numberbit valuebit description
0-2acknowledge value1- means acknowledge, no error
2- means wait, target not ready
4- means fault or error
7- typically means the target is disconnected

SWD Read and Write Details.

The SWD port supports reading and writing to the Debug Port and the Access Port. The Cortex Debug Port consists of 4 32-bit registers. When executing an SWD transaction, a Debug Port transaction is specified by leaving bit 1 (port select) set to zero during the request phase of the SWD transaction. The address is specified by bits 3 and 4. Read is specified by setting bit 2 as 1, writes by clearing bit 2 to 0. Writes do not actually complete until after the following SWD command or until receiving a “flush” which is simply eight 0s clocked out onto SWDIO. The Cortex Access Port address space has 64 32-bit registers. Because only two bits of address are specified in the SWD request phase, four more bits of address need to be set by using the AP Select register at address 8 on the Debug Port. To execute a transaction on the Access Port, typically
the Debug Port AP Select register must be written first before the Access Port is written. When executing a read on the Access Port, the result returned will be that of the previous read. Therefore when executing a read operation, a 2nd dummy read must be done to get the results. If executing a sequence of reads, only one dummy read is needed to get the first result. There is no need for a dummy read between every read in
a sequence.

Please note that both the Debug Port and the Access Port are NOT part of the Cortex CPU core’s general address space. These ports and their registers only exist inside the SWD debug port. For details on these registers and their uses please see the ARM Debug Interface v5 Architecture Specification documentation and errata.

Initializing SWD.

The SWD protocol allows full control of an LPC microcontroller. Because of this, it is critical that the port be insensitive to noise under a wide range of design conditions. To make the SWD port insensitive to noise, an unlock or connection sequence must be executed before the port can be used. The unlock sequence consists of several different steps.

SWD Unlock Sequence Steps

step numberdescription
1The Host needs to switch the target from JTAG to SWD mode by clocking 0xE79E onto SWDCLK/SWDIO
2SWD connection sequence- clock out more than 50 binary 1s
3Must read the Debug Port IDCODE register (address 0)
4Turn on Debug Port by settings bits 28 and 30 at DP address 4
5Write AP select (debug port address 8) to 0xF0 (to prep for AP read of 0xFC)
6Unlock Access Port by reading AP ID register (AP address 0xFC)

Part Two
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Diagrams
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Hi, Did you finish read

Hi,
Did you finish read IDCODE? I meet the same issue.

Hi. I try to repeat this

Hi. I try to repeat this and got a problem.

* It's look like target switch "from JTAG to SWD mode by clocking 0xE79E" OK (*).
* Then I send about 64 binary 1s.
* But I do not receive any ack on Debug Port IDCODE register read (see Read_IDCODE.png).
---
(*) During first send 0xE79E at power up I have extra thick 0's at falling edges of SWCLK (see Send_0xE79E.png). But all next attempting to connect have no this ticks. I think this becouse of JTAG turned on. Am I right?

As host I use open-drain and external pull-up resistor (and other micro-controller, not lpc11u14). As target LPC1343 on LPCXpresso (LPC-link on board but no USB connection). Code based on sources from Part Four ported to my mocro-controller. Output DIO before CLK (not parallel like in part four).
I try with and without sending extra 1's and 0's (like in sources at part four) - no matter. With pushed reset and at run. The same result.

Any idea?

P.S.: Thank you for your posts.

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