LPC43xx dual-core FreeRTOSx2 project with IPC

LPC43xx dual-core FreeRTOSx2 project with IPC

wellsk's picture

This is another LPC43xx dual-core project for use with the Keil uVision 4 tools.

This project runs FreeRTOS on both cores and uses a shared memory queue and interrupt signalling to each core for event management and control of the tri-color LED.

More information on the project can be found here: http://www.lpcware.com/content/project/lpc43xx-dual-core-notes

Please report problems, bugs, improvements, hints, etc. on the comment form on the project page.

The FreeRTOSV7.1.0-cm0_extra.zip file included here are some edits to the CM0 port for RVDS and the use of an alternate timer tick. You'll also need this to build the M0 version of the proejct.

 

NOTE: You need the v4 version of the Hitex board to use the demo.

 

Known issues

The pins for configuring external FLASH are not setup as part of the project. See the comment section of this page for specific details and the changed files.

 

Update history

04/27/2012    Original release

05/01/2012    Updared release with FLASH boot support

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This project is now obsolete.

This project is now obsolete. Updated dual-core projects for Keil, IAR, and Xpresso are here:
http://lpcware.com/content/nxpfile/lpcopen-platform

These updates fix an issue

These updates fix an issue with the FLASH configuration with image sizes larger than 16K.

*snip*
The bootloader configures only A[13:0] for the boot process. If you have more than 16kbyte of code you need to configure more address lines.
There is no configuration of the external memory interface in the project, besides the settings the bootloader is doing.
The correct place to do this configuration is before main(). In the attached files you see that the address pins are configured in the startup file in assembler.
*snip*

PreviewAttachmentSize
system_LPC43xx.c8.13 KB
startup_LPC43xx.s12.87 KB
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