256Mbit Flash with SPIFI

I seem to remember reading something in the errata about SPIFI. I think it had to do with only being able to boot from it. Something to do with only being able to boot from the lower address numbers. The work around, if I remember, was to make boot code in the initial section of the SPIFI that copies your code out of the Flash and into working ram for you.

Looking at the Users Manual The addresses for SPIFI are:
(64 MB) 0x1400 0000 to 0x17FF FFFF
(128 MB)0x8000 0000 to 0x87FF FFFF (Non debugable area)

The manual doesn't explain a lot about it, but it looks like the first half of the 128 is actually the same data as the first 64 MB (0x1400 0000 to 0x17FF FFFF).
It also says that if you read from these locations that the SPIFI generates the command to do so for you. (It is read only)
You will also have to make sure that your chip works with the command set that the SPIFI uses.

If you learn any more about the SPIFI & serial flash please post about it, as eventually I am going to have to figure it out too.

This reminded me of a processor I worked on long ago (don't remember which processor), but for that one the boot code had to be in the first page of the highest memory bank because all the "spare" address lines were pulled high until the boot code could activate them.