LPC11xx main clock limit

I believe the data sheet says 50MHz. My Code Red startup file sets it to 48MHz by default.

Jerry,

Can you tell me where did you find it in the data sheet?

I know that the max system clock is 50MHz, that's clearly stated.
But I could not find the limit on the main clock. I went through the user manual and found nothing.

Ah, you mean the PLL output? Don't know what that is, for now I'm just leaving everything set to the default 48MHz.

According to the Rev 6 user manual 'main clock (FCLKOUT)' needs to be less the 100 MHz.

And it's really working.

CLKOUT is showing a 96 MHz main clock.

Still don't know how to delete....

100MHz it is.

Thanks a lot!

look in UM10398a.pdf, page 43.

The block diagram of this PLL is shown in Figure 7. The input frequency range is 10 MHz
to 25 MHz. The input clock is fed directly to the Phase-Frequency Detector (PFD). This
block compares the phase and frequency of its inputs, and generates a control signal
when phase and/ or frequency do not match. The loop filter filters these control signals
and drives the current controlled oscillator (CCO), which generates the main clock and
optionally two additional phases. The CCO frequency range is 156 MHz to
320 MHz.These clocks are either divided by 2xP by the programmable post divider to
create the output clock(s), or are sent directly to the output(s). The main output clock is
then divided by M by the programmable feedback divider to generate the feedback clock.
The output signal of the phase-frequency detector is also monitored by the lock detector,
to signal when the PLL has locked on to the input clock.

Remark: The divider values for P and M must be selected so that the PLL output clock
frequency FCLKOUT is lower than 100 MHz.

OK, I'm getting blind, it seems.
I've read that chapter umpteen times (searching for the value) and missed that remark every time.
Thanks.