As far as I can tell, the SSP on the LPC chips is a standard ARM macrocell.
However, the NXP docs does not mention the test registers what the ARM docs describe.
They are extremely handy when you have to run the SSP as a slave.
If you expect to send some data to the master and you load it to the FIFO, then if the master prematurely aborts the transfer your FIFO will not be flushed.
There is no mechanism to actually FLUSH the FIFO, thus from that point on all frames will be off.
The test registers allow you to actually flush the transmit FIFO in such situations.
I wonder if the test registers are implemented but omitted from the NXP manuals or the test mode is not realised on the silicon at all?
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