CDL boot loader introduction
The u-boot boot loader cannot be booted directly from the LPC32x0 boot ROM. Instead, a small loader program must be used to initialize the memory used by u-boot and then load it from it's non-volatile storage into memory before executing it. Because u-boot loads and executes from SDRAM, this initial loader must also initialize SDRAM.
The CDL provides a reference boot loader called the kickstart loader that is meant to be the primary boot image loaded from the LPC3250 boot ROM. The kickstart loader can reside in NAND, NOR, or SPI FLASH and can be configured to load an image from any source into any address with any size. More information about the LPC32x0 boot process can be found on the LPC32x0 boot process page or in the LPC32x0 User's guide.
The CDL has been ported to the Phytec, Embedded Artists, and Future Designs boards.
Kickstart loader and stage 1 definitions
The terms kickstart loader and stage 1 application are used to describe the bootable images for the LPC32x0.
A stage 1 application is the application we would ideally like to start when the LPC32x0 is reset or powered up. Stage 1 applications include programs such as u-boot, e-boot, or another full-featured application. Unfortunately, most stage 1 applications are too big to be directly booted by the LPC32x0 boot ROM. For systems where the stage 1 application can’t be directly booted, a smaller ‘kickstart’ boot loader is required to boot from the LPC32x0 boot ROM and then continue loading and start execution of the stage 1 application.
For systems that boot from large block NAND FLASH or SPI FLASH, the maximum boot image size is 54K. If the application to be loaded exceeds this size or if the application needs to be loaded anywhere besides IRAM, the kickstart loader is required. The kickstart loader will in turn load the stage 1 application and transfer control to it after it has been loaded. If the application to be loaded is smaller than 54K and resides in IRAM, the stage 1 application can be directly loaded from the boot ROM instead of being routed through the kickstart loader.
For systems that boot from small block NAND FLASH, the maximum boot image size is 15.5K.
For systems that boot from NOR FLASH, no kickstart loader is needed (in most cases). The stage 1 application can be executed directly from NOR FLASH.
The kickstart loader must be developed to be smaller than 54K (15.5K for systems that boot from small block NAND FLASH). This loader can include startup code that sets up the board’s initial GPIO states and muxes, setup the initial clocking, setup a basic MMU table if needed, setup all the memory interface, and then load an image and transfer control to that image.
For small block NAND systems with the 15.5K boot image limit, this can be tough to manage. Tradeoffs may need to be made on what functions can be handled by the kickstart loader. Enabling all the functions may make a kickstart image that exceeds 15.5K. The image size would have to be reduced in this case by removing features from the kickstart loader and moving them to the stage 1 application. If your stage 1 application needs to execute in SDRAM, but the kickstart is too large with all the SDRAM init code, then code needs to be rearranged or aggressively optimized to meet the boot image size limitation.
Kickstart loader bootup procedure
The following sequence shows how the LPC32x0 handles kickstart load and transfer from the boot ROM using NAND or SPI FLASH.
- LPC32x0 processor is reset
- LPC32x0 boot ROM interrogates boot devices
- For SPI FLASH, the image loaded at SPI FLASH offset 8 is loaded into IRAM at address 0x0
- For NAND FLASH, the image loaded in page 1 of block 0 or 1 is loaded into IRAM at address 0x0
- After the image is loaded, the boot ROM transfers control to the image’s startup code loaded at address 0x0
Stage 1 applications
Stage 1 applications are applications that meet one of the following criteria:
- Loads and executes directly from the UART into IRAM
- Loads and executes from the kickstart loader in IRAM or SDRAM
- Loads and executes in place from NOR FLASH
For Linux, u-boot can be considered a stage 1 application. For the Phytec and Embedded Artists boards, the kickstart loader loads S1L as the stage 1 application. S1L initializes the board functions such as clocking and SDRAM and then loads and starts u-boot. Optionally, the kickstart loader can use u-boot as the stage 1 application bypassing S1L.
Stage 1 Loader
The Stage 1 Loader (S1L) is an optional stage 1 application that provides debug, monitor, and boot support for an NXP micro controller. It can be used as the initial boot image the micro controller executes and then configured to load another image automatically. S1L is included free as part of the LPC32x0 CDL and is pre-installed on the Embedded Artist and Phytec LPC3250 based development boards. It can also be installed on Future Design LPC3250 based boards.
The main features of the stage 1 loader are shown below:
- Register and memory change and dump
- Poke, peek, dump, fill
- Image load via a serial port , SDMMC card, or FLASH
- Supports raw binary and S-record files
- Images can be executed after loading
- Images can be saved in NAND FLASH
- NAND FLASH support
- Erase of NAND blocks
- Direct read and write of FLASH blocks and pages
- Bad block management
- MMU functions
- Data and instruction cache control
- Virtual address translation enable/disable
- Virtual address remapping
- Page table dump
- System support functions
- Baud rate control, clock control, system information
- Automatic load and run support
- Automatic load and execution of images from NAND FLASH, SDMMC, or via the terminal
- Testing functions
- SDRAM memory tests, bandwidth tests
- SDRAM calibration and configuration data
Other features of the CDL
This CDL provides a generic set of drivers which highlight how specific peripherals and functions work. The CDL also provides Board Support Packages (BSP) for development boards based on the LPC32x0 microcontrollers. The BSPs provide reference code for system startup including boot loaders, system clock setup, SDRAM setup, and MMU/cache setup.
The CDL provides the following features:
- Various drivers and header files for the LPC32x0 microcontroller
- Common software and definitions for LPC32x0 microcontrollers
- Support for Keil uVision4, ARM Realview 3.1, and GNU CodeSourcery tool chains
- BSPs for Embedded Artists, Phytec, and Future Designs LPC3250 based development boards
- A reference BSP for the NXP LPC32x0 based validation and reference platform
- A generic BSP that contains universal startup code for easy porting to a new LPC32x0 based platform
- Free for use with NXP LPC32x0 microcontrollers
The Phytec, Embedded Artists, and Future Designs LPC3250 BSPs provide the following features:
- Startup code and board initialization code based on the board’s possible boot modes and devices
- Software to re-burn the boot loaders into NAND, SPI, or NOR FLASH
- Updated versions of the kickstart loader and S1L applications
- Tool-less software deployment options when used with the Stage 1 Loader or the Serial Loader
- Various peripheral examples that can downloaded and executed via S1L or a debugger
- Quickstart instructions
The NXP LPC32x0 validation and reference platform is not commercially available, although the code included in the BSP is provided as part of the CDL. A generic LPC32x0 BSP is also provided as part of this CDL. This generic BSP provides the following features:
- Configurable startup code and board initialization code
- Standard and mobile single and double data rate SDRAM reference code based on the JEDEC SDRAM initialization sequence
- Reference drivers for small and large block NAND FLASH using the MLC and SLC controllers
- SPI FLASH and NOR FLASH reference drivers
- Burner software for burning and updating images in NAND, SPI, or NOR FLASH
- Various kickstart loader and S1L examples for multiple deployment methods
- Ideal for new board bringup (support for IRAM only boot via the Serial loader tool)
- Documentation that explains the reasoning and structure of the software