Frequently Asked Questions

Refer to the AN10974 LPC176x/175x 12-bit ADC design guidelines: http://www.nxp.com/documents/application_note/AN10974.pdf

The LPC13xx and LPC17xx families have a single ADC and sample-and-hold, so sampling multiple signals at the same time is not possible, unless an external sample-and-hold circuit is utilized.
The LPC18xx microcontrollers are a high performance Cortex-M3 family that has two ADCs, so it would be possible to sample multiple signals at the same time with these devices. The LPC43xx Cortex-M4 devices would also be an option since they also contain multiple ADCs.

SNR characterization has not been done for LPC1700 ADC.

The LCD DMA keeps the LCD FIFO full. It can only DMA from the LCD framebuffer which must be a contiguous block of memory. Scatter-gather support isn't provided, but due to the nature of how the frame buffer must be arranged (in physical memory), scatter-gather support isn't really needed.

Touch screen support for analog touch panels is available, including a low level driver, which handles the analog input (from an 8 bit or better AD-converter), debouncing and calibration of the touch screen. The window manager deals with touch messages and widgets such as button objects. It takes no more than one line of code to create a button or another widget, which then automatically handles touch messages and reacts accordingly. emWin also supports mouse and keyboard inputs.

The touch screen simulation is integrated into the regular emWin simulation. Mouse events are used to simulate the touch screen. The simulation can be used to write the user interface of your application and can be sent as a simple .exe files to anybody for discussion, demonstration or verification.

The PC simulation of emWin allows you to compile the same "C" source on your Windows PC using a native (typically Microsoft) compiler and create an executable for your own application. The resulting executable can be easily sent via email. With the simulator, you can design the user interface on your PC (no need for hardware!), debug your user interface program, and create demos of your application, which can be used to discuss the user interface.

A variety of different fonts are shipped with the basic software: 4*6, 6*8, 6*9, 8*8, 8*9, 8*16, 8*17, 8*18, 24*32, and proportional fonts with pixel-heights of 8, 10, 13, 16. New fonts can be defined and simply linked in. Only the fonts used by the application are actually linked to the resulting executable, resulting in minimum ROM usage. Fonts are fully scalable, separately in X and Y. Font converter available; any font available on your host system (i.e. Microsoft Windows) can be converted.

emWin is compatible with single-task and multitask environments, and proprietary operating system or any commercial RTOS, including uCLinux.

An RTOS is not required to use emWin. It works as a stand-alone library or can be incorporated into your RTOS.

emWin has been designed to have a memory footprint as small as possible. Various configuration switches allow tailoring the software to perfectly match your needs, reducing memory consumption to a minimum. The memory requirements vary depending on which parts of the software are used and how efficient your target compiler is, as well as whether the libraries are optimized for speed or for size. It is therefore not possible to specify precise values, but the following applies to typical systems, according to Segger.com :
Small systems (no window manager)
• RAM: 100 bytes
• Stack: 500 bytes
• ROM: 10-25 kb (depending on the functionality used)
Big systems (incl. window manager and widgets)
• RAM: 2-6kb (depending on number of windows required)
• Stack: 1200 bytes
• ROM: 30-60kb (depending on on the functionality used)

The maximum display resolution is limited by the LCD controller, the CPU bandwidth, the buffers, and the external bus speeds, as well as the panel size, the color depth and the refresh rates. Use the LCD Controller Bandwidth calculator on LPCware.com to determine your LCD parameters.

LPC247x bus bandwidth calculator:
http://www.lpcware.com/content/nxpfile/lpc247x-lcd-bus-load-calculator

LPC178x and LPC40xx bus bandwidth calculator:
http://www.lpcware.com/content/nxpfile/lcd-bus-bandwidth-calculator-lpc1...

LPC18xx and LPC43xx bus bandwidth calculator:
http://www.lpcware.com/content/nxpfile/lcd-bandwidth-calculator-lpc18xx-...

The porting guide on LPCware.com will show you how to change the Board Support Packages to work with other LCD panels.

NXP has installers for ARM/Keil, IAR, Rowley Crossworks and LPCXpresso on LPCware.com. Support for other compilers may be added in the future if demand warrants.

The emWin source code is available directly from Segger at a discount from the normal price for NXP users. Please go to www.segger.com or email support@segger.com for details.

Send an email to register@segger.com with:
Company name and address
Your name
Your job title
Your email address and telephone number
Name and version of the product
Note that there likely will be some delay between Segger updates to emWin and those updates being incorporated into the NXP installers on LPCware.com.

The emWin software is not pre-loaded on any standard development boards. Instead, download the software from the LPCware site and follow the instructions in the Start-up guide to run emWin on NXP development boards.

For support on the NXP emWin installers and examples, please use the LPCware.com forum or contact NXP support. For any standard emWin questions, please contact Segger or use their emWin site: http://www.segger2.com/index.php?page=Board&boardID=3&s=9cf50301c3e3d621...

The free emWin software is the same as the standard emWin software that can be purchased from Segger. The examples on the LPCware website in the installer are written for the NXP microcontrollers and evaluation boards.

Yes, the licensed emWin software can be used with any NXP microcontroller, even if it doesn’t have an LCD controller. Customers may use the emWin software with SPI-interfaced LCD panels and NXP LPC1100 Cortex-M0 microcontroller, for example.

Currently there are BSP’s available for LPC1788 boards, supporting the different panel sizes that attach to this board and different compilers/IDEs. Additional BSP’s are being added for other series and will be added to the LPCware.com emWin site in the future.

Users are able to use the licensed emWin software for any NXP Cortex-M0, Cortex-M3, Cortex-M4, ARM7 or ARM9 microcontroller. Please refer to the license agreement for details. The license agreement is installed with the emWin software.
Additional emWin details can be found at http://www.lpcware.com/content/project/emwin-graphics-library

There is a click-through license that has to be agreed to before the software can be downloaded in the Board Support Package on LPCware.com. No other licenses need to be signed or agreed to unless you need source code or additional support from Segger.

The software can be downloaded from the LPCware website.
http://www.lpcware.com/content/project/emwin-graphics-library

You can use emWin with any open source license that does not require the source code of emWin to also be released and licensed under the same open source license terms. For example, the modified GPL license for FreeRTOS explicitly adds an exception that any linked libraries are excluded from the open source license terms. Unmodified GPL licenses do not have this exception, so the free emWin could not be used with an unmodified GPL license. The increasingly popular BSD-style licenses place no restrictions on any other parts of the firmware that might be linked in with the BSD-licensed code. BSD-licensed code can be used with emWin because there are no requirements to release the emWin source and place it under similar license terms. Please refer to the license agreement for specific details.

NXP customers may use emWin for development and production completely royalty-free as long as it is used on an NXP microcontroller. The license is part of the board support package .zip file on LPCware.com . Please refer to the license agreement for details.
emWin for NXP microcontrollers can be found at http://www.lpcware.com/content/project/emwin-graphics-library

I've placed a few possible links below, but you can Google "convrom.c" to get other sites.

http://code.ohloh.net/search?s=convrom.c&browser=Default
http://trac.umnaem.webfactional.com/browser/trunk/Hardware/eCos/packages...

Once you've created a SWIM window, there are several image related SWIM functions for placing image data into a window.

Before you can use those functions, you need to have a 2D array of pixel data in the LCD's native display format for your image. For example, if you are using RGB565 color (and SWIM should be configured for RGB565 color) and you have a 320x240 pixel image you want to display, you need to provide a pointer to that image data that is at 320x240@RGB565. If you have a BMP image, you can use the BMP to C converter  to convert a BMP image to C code in the native display format. You can compile this image data directly into your code.

Once you have the image data and the dimensions of the image, you can use one of the 4 SWIM functions below to display it. If you use a scaled function, the image will be scaled to the window size regardless of it's dimensions. Scaling usually requires adding or removing pixels to get the image to fit in the window. The non-scaled options will clip one or more sides of the image to fit inside the window. For the non-scaled option, an image smaller than the window will not alter window data outside its image. Finally, the SWIM functions also allow you to rotate an image in the window at 90, 180, and 270 degrees.

Example:

An image stored in RGB565 color format is stored in memory pointed to by the variable 'imagedata'. The image is 400x300 pixels in size.

A window with size 640x480 has been created and is pointed to by the win1 variable.

To display the image in the full window scaled to the windows size, use the following function:

   swim_put_scale_image(&win1, imagedata, 400, 300);

SWIM functions:

/* Image rotation tags */
typedef enum {NOROTATION, RIGHT, INVERT, LEFT} SWIM_ROTATION_T;

/***********************************************************************
 * Image drawing functions
 **********************************************************************/

/* Puts a raw image into a window */
void swim_put_image(SWIM_WINDOW_T *win,
                    const COLOR_T *image,
                    INT_32 xsize,
                    INT_32 ysize);

/* Puts a raw image into a window inverted */
void swim_put_invert_image(SWIM_WINDOW_T *win,
                           const COLOR_T *image,
                           INT_32 xsize,
                           INT_32 ysize);

/* Puts a raw image into a window rotated left */
void swim_put_left_image(SWIM_WINDOW_T *win,
                         const COLOR_T *image,
                         INT_32 xsize,
                         INT_32 ysize);

/* Puts a raw image into a window rotated right */
void swim_put_right_image(SWIM_WINDOW_T *win,
                          const COLOR_T *image,
                          INT_32 xsize,
                          INT_32 ysize);

/* Puts and scales a raw image into a window */
void swim_put_scale_image(SWIM_WINDOW_T *win,
                          const COLOR_T *image,
                          INT_32 xsize,
                          INT_32 ysize);

/* Puts and scales a raw image into a window inverted */
void swim_put_scale_invert_image(SWIM_WINDOW_T *win,
                                 const COLOR_T *image,
                                 INT_32 xsize,
                                 INT_32 ysize);

/* Puts and scales a raw image into a window rotated left */
void swim_put_scale_left_image(SWIM_WINDOW_T *win,
                               const COLOR_T *image,
                               INT_32 xsize,
                               INT_32 ysize);

/* Puts and scales a raw image into a window rotated right */
void swim_put_scale_right_image(SWIM_WINDOW_T *win,
                                const COLOR_T *image,
                                INT_32 xsize,
                                INT_32 ysize);

/* One API for all the functions */
void swim_put_win_image(SWIM_WINDOW_T *win,
                        const COLOR_T *image,
                        INT_32 xsize,
                        INT_32 ysize,
                        INT_32 scale,
                        SWIM_ROTATION_T rtype);

 

Sorry, there is no specific code in the LPC18xx PDL. However, a SPI driver example is there as a starting point.

If it happens, a DMA underflow will occur causing a tear. For the frame being rendered when this happens, the data under the spot of the display where the tear happen will be misaligned. Because the frame is being updated at a high rate (60Hz?), you see a quick flicker on the display. If the tear happens a lot, the flicker can be annoying.
It should be noted that the LCD controller will underflow only when it's DMA request is stalled for a considerable amount of time. The LCD controller has it's own buffer memory filled up by DMA and can handle short stalls during it's DMA request.

Not necessarily, it really depends on the LCD resolution, clock rate, etc. Using a 16-bit interface will have more of a chance for tearing and won't be able to handle as big a display as a 32-bit interface.

The size limit for the LCD frame buffer is 1024x1024x4, which would be a 1k x 1k x 24bpp display. You can compute a frame buffers memory requirements by multiplying the X resolution by the Y resolution by the color depth in bytes. For example, a 320x240 display at 16bpp (2bytes per pixel) would need 320x240x2 = about 150kB. You can also use the bandwidth calculator to compute this value.

LPC247x bus bandwidth calculator:
http://www.lpcware.com/content/nxpfile/lpc247x-lcd-bus-load-calculator

LPC178x and LPC40xx bus bandwidth calculator:
http://www.lpcware.com/content/nxpfile/lcd-bus-bandwidth-calculator-lpc1...

LPC18xx and LPC43xx bus bandwidth calculator:
http://www.lpcware.com/content/nxpfile/lcd-bandwidth-calculator-lpc18xx-...

The signals are not LVDS. You'll need a converter if you are using a display with an LVDS interface.

As far as I know, there isn't a list. But almost any TFT with the common TFT signals should work fine. These include displays from Sharp, Hitachi, and many more manufacturers.

The internal RAM is not dedicated for video memory. All memory - external or internal - can be shared with the LCD controller.

Only if the OLED LCD supports TFT timing. I don't think OLED displays do that. From my brief look at them, they had their own frame buffer integrated into the panel with a connection (ie, SPI) to update that memory.

SWIM is a "Simple Windows Interface Manager". It basically provides non-overlapping window regions with simple graphics primitives and text operations. It's easy to use, a great learning tool, and it's free.

The LCD controller is it's own bus master and isn't part of the GP DMA module. DMA operation for the LCD controller is pretty much transparent - all you need to do is setup the LCD controller and point the frame buffer to an address.

If the LCD controller has higher priority than the other devices that use the EMC, the other devices will be delayed until they can get the EMC bus. In the case of the CPU, the CPU will stall until it can get the bus. Unless the DMA request rate is very high, the CPU stalls shouldn't impact performance too much.

The frame buffer can be in any contiguous block of memory. This could include a block of internal SRAM or in external SDRAM or SRAM. Usually, the frame buffer storage requirement (depends on LCD resolution and colors) is too large to fit in internal SRAM and external SDRAM is used.

You can run up to 1024x768 at 24bpp as long as the bandwidth can be maintained by the LPC1788 and the DMA doesn't underflow. Unless you're driving that display size at a very low refresh rate, that specific configuration may not be feasible, as the bandwidth requirements will be higher than the LCP1788 can maintain. We offer a bandwidth calculator to help figure out if a specific configuration will be viable.

Question:
If the RMII interface is provided to the physical transmission medium (PHY) and this provided a reference clock to the MAC (that is integrated into the microcontrollers) and operated at a tenth of the expected speed (i.e. 5MHz), would everything still work (the data communication system is intended to operate as 10Mb/s Ethernet, but at reduced data rate of 1Mb/s)?

Answer:
Running at a slower reference clock should still work, however it is not guaranteed.

Please see http://lpcware.com/content/blog/lpc2300-and-lpc2400-rev-b-rev-d-change-e... for details regarding the change from Rev B to Rev D silicon differences.

Reading part IDs are the recommended way of determining the MAC IDs on different parts.

The Ethernet PHY configuration is a one-time event. Once the configuration has been completed using MDIO and MCLK, these pins will no longer be required. It will then be possible to switch the pin function to USB.
Another option is to use Ethernet MII Management (MDIO) using software. This is described in Application note AN10859.
http://www.lpcware.com/content/nxpfile/an10859-lpc1700-easyweb
If MDIO is implemented in software, there will be no need to share pins between USB and Ethernet.

Ethernet bootloaders are available as part of the Flash Magic tool ( www.flashmagictool.com). After installing Flash Magic, you can find the bootloader in the Flash Magic\Ethernet Bootloader directory (C:\Program Files (x86)\Flash Magic\Ethernet Bootloader in a Windows x64 environment). An application note is available for download from http://www.lpcware.com/content/nxpfile/an10744-ethernet-secondary-isp-bo...

SWIM only works in the native display’s memory format and won’t write in landscape format on a portrait frame buffer configuration.

However, as a workaround, you can generate a dummy frame buffer in landscape format and use SWIM to write to that and then occasionally copy that buffer to the real portrait frame buffer, reorganizing the pixels in the copy. This won’t be fast, but it will allow evaluation of SWIM in landscape mode.

Something like this:

Touch screen support for analog touch panels is available, including a low level driver, which handles the analog input (from an 8 bit or better AD-converter), debouncing and calibration of the touch screen. The window manager deals with touch messages and widgets such as button objects. It takes no more than one line of code to create a button or another widget, which then automatically handles touch messages and reacts accordingly. emWin also supports mouse and keyboard inputs.

The touch screen simulation is integrated into the regular emWin simulation. Mouse events are used to simulate the touch screen. The simulation can be used to write the user interface of your application and can be sent as a simple .exe files to anybody for discussion, demonstration or verification.

The PC simulation of emWin allows you to compile the same "C" source on your Windows PC using a native (typically Microsoft) compiler and create an executable for your own application. The resulting executable can be easily sent via email. With the simulator, you can design the user interface on your PC (no need for hardware!), debug your user interface program, and create demos of your application, which can be used to discuss the user interface.

A variety of different fonts are shipped with the basic software: 4*6, 6*8, 6*9, 8*8, 8*9, 8*16, 8*17, 8*18, 24*32, and proportional fonts with pixel-heights of 8, 10, 13, 16. New fonts can be defined and simply linked in. Only the fonts used by the application are actually linked to the resulting executable, resulting in minimum ROM usage. Fonts are fully scalable, separately in X and Y. Font converter available; any font available on your host system (i.e. Microsoft Windows) can be converted.

emWin is compatible with single-task and multitask environments, and proprietary operating system or any commercial RTOS, including uCLinux.

An RTOS is not required to use emWin. It works as a stand-alone library or can be incorporated into your RTOS.

emWin has been designed to have a memory footprint as small as possible. Various configuration switches allow tailoring the software to perfectly match your needs, reducing memory consumption to a minimum. The memory requirements vary depending on which parts of the software are used and how efficient your target compiler is, as well as whether the libraries are optimized for speed or for size. It is therefore not possible to specify precise values, but the following applies to typical systems, according to Segger.com :
Small systems (no window manager)
• RAM: 100 bytes
• Stack: 500 bytes
• ROM: 10-25 kb (depending on the functionality used)
Big systems (incl. window manager and widgets)
• RAM: 2-6kb (depending on number of windows required)
• Stack: 1200 bytes
• ROM: 30-60kb (depending on on the functionality used)

The maximum display resolution is limited by the LCD controller, the CPU bandwidth, the buffers, and the external bus speeds, as well as the panel size, the color depth and the refresh rates. Use the LCD Controller Bandwidth calculator on LPCware.com to determine your LCD parameters.

LPC247x bus bandwidth calculator:
http://www.lpcware.com/content/nxpfile/lpc247x-lcd-bus-load-calculator

LPC178x and LPC40xx bus bandwidth calculator:
http://www.lpcware.com/content/nxpfile/lcd-bus-bandwidth-calculator-lpc1...

LPC18xx and LPC43xx bus bandwidth calculator:
http://www.lpcware.com/content/nxpfile/lcd-bandwidth-calculator-lpc18xx-...

The porting guide on LPCware.com will show you how to change the Board Support Packages to work with other LCD panels.

NXP has installers for ARM/Keil, IAR, Rowley Crossworks and LPCXpresso on LPCware.com. Support for other compilers may be added in the future if demand warrants.

The emWin source code is available directly from Segger at a discount from the normal price for NXP users. Please go to www.segger.com or email support@segger.com for details.

Send an email to register@segger.com with:
Company name and address
Your name
Your job title
Your email address and telephone number
Name and version of the product
Note that there likely will be some delay between Segger updates to emWin and those updates being incorporated into the NXP installers on LPCware.com.

The emWin software is not pre-loaded on any standard development boards. Instead, download the software from the LPCware site and follow the instructions in the Start-up guide to run emWin on NXP development boards.

For support on the NXP emWin installers and examples, please use the LPCware.com forum or contact NXP support. For any standard emWin questions, please contact Segger or use their emWin site: http://www.segger2.com/index.php?page=Board&boardID=3&s=9cf50301c3e3d621...

The free emWin software is the same as the standard emWin software that can be purchased from Segger. The examples on the LPCware website in the installer are written for the NXP microcontrollers and evaluation boards.

Yes, the licensed emWin software can be used with any NXP microcontroller, even if it doesn’t have an LCD controller. Customers may use the emWin software with SPI-interfaced LCD panels and NXP LPC1100 Cortex-M0 microcontroller, for example.

Currently there are BSP’s available for LPC1788 boards, supporting the different panel sizes that attach to this board and different compilers/IDEs. Additional BSP’s are being added for other series and will be added to the LPCware.com emWin site in the future.

Users are able to use the licensed emWin software for any NXP Cortex-M0, Cortex-M3, Cortex-M4, ARM7 or ARM9 microcontroller. Please refer to the license agreement for details. The license agreement is installed with the emWin software.
Additional emWin details can be found at http://www.lpcware.com/content/project/emwin-graphics-library

There is a click-through license that has to be agreed to before the software can be downloaded in the Board Support Package on LPCware.com. No other licenses need to be signed or agreed to unless you need source code or additional support from Segger.

The software can be downloaded from the LPCware website.
http://www.lpcware.com/content/project/emwin-graphics-library

You can use emWin with any open source license that does not require the source code of emWin to also be released and licensed under the same open source license terms. For example, the modified GPL license for FreeRTOS explicitly adds an exception that any linked libraries are excluded from the open source license terms. Unmodified GPL licenses do not have this exception, so the free emWin could not be used with an unmodified GPL license. The increasingly popular BSD-style licenses place no restrictions on any other parts of the firmware that might be linked in with the BSD-licensed code. BSD-licensed code can be used with emWin because there are no requirements to release the emWin source and place it under similar license terms. Please refer to the license agreement for specific details.

NXP customers may use emWin for development and production completely royalty-free as long as it is used on an NXP microcontroller. The license is part of the board support package .zip file on LPCware.com . Please refer to the license agreement for details.
emWin for NXP microcontrollers can be found at http://www.lpcware.com/content/project/emwin-graphics-library

I've placed a few possible links below, but you can Google "convrom.c" to get other sites.

http://code.ohloh.net/search?s=convrom.c&browser=Default
http://trac.umnaem.webfactional.com/browser/trunk/Hardware/eCos/packages...

Once you've created a SWIM window, there are several image related SWIM functions for placing image data into a window.

Before you can use those functions, you need to have a 2D array of pixel data in the LCD's native display format for your image. For example, if you are using RGB565 color (and SWIM should be configured for RGB565 color) and you have a 320x240 pixel image you want to display, you need to provide a pointer to that image data that is at 320x240@RGB565. If you have a BMP image, you can use the BMP to C converter  to convert a BMP image to C code in the native display format. You can compile this image data directly into your code.

Once you have the image data and the dimensions of the image, you can use one of the 4 SWIM functions below to display it. If you use a scaled function, the image will be scaled to the window size regardless of it's dimensions. Scaling usually requires adding or removing pixels to get the image to fit in the window. The non-scaled options will clip one or more sides of the image to fit inside the window. For the non-scaled option, an image smaller than the window will not alter window data outside its image. Finally, the SWIM functions also allow you to rotate an image in the window at 90, 180, and 270 degrees.

Example:

An image stored in RGB565 color format is stored in memory pointed to by the variable 'imagedata'. The image is 400x300 pixels in size.

A window with size 640x480 has been created and is pointed to by the win1 variable.

To display the image in the full window scaled to the windows size, use the following function:

   swim_put_scale_image(&win1, imagedata, 400, 300);

SWIM functions:

/* Image rotation tags */
typedef enum {NOROTATION, RIGHT, INVERT, LEFT} SWIM_ROTATION_T;

/***********************************************************************
 * Image drawing functions
 **********************************************************************/

/* Puts a raw image into a window */
void swim_put_image(SWIM_WINDOW_T *win,
                    const COLOR_T *image,
                    INT_32 xsize,
                    INT_32 ysize);

/* Puts a raw image into a window inverted */
void swim_put_invert_image(SWIM_WINDOW_T *win,
                           const COLOR_T *image,
                           INT_32 xsize,
                           INT_32 ysize);

/* Puts a raw image into a window rotated left */
void swim_put_left_image(SWIM_WINDOW_T *win,
                         const COLOR_T *image,
                         INT_32 xsize,
                         INT_32 ysize);

/* Puts a raw image into a window rotated right */
void swim_put_right_image(SWIM_WINDOW_T *win,
                          const COLOR_T *image,
                          INT_32 xsize,
                          INT_32 ysize);

/* Puts and scales a raw image into a window */
void swim_put_scale_image(SWIM_WINDOW_T *win,
                          const COLOR_T *image,
                          INT_32 xsize,
                          INT_32 ysize);

/* Puts and scales a raw image into a window inverted */
void swim_put_scale_invert_image(SWIM_WINDOW_T *win,
                                 const COLOR_T *image,
                                 INT_32 xsize,
                                 INT_32 ysize);

/* Puts and scales a raw image into a window rotated left */
void swim_put_scale_left_image(SWIM_WINDOW_T *win,
                               const COLOR_T *image,
                               INT_32 xsize,
                               INT_32 ysize);

/* Puts and scales a raw image into a window rotated right */
void swim_put_scale_right_image(SWIM_WINDOW_T *win,
                                const COLOR_T *image,
                                INT_32 xsize,
                                INT_32 ysize);

/* One API for all the functions */
void swim_put_win_image(SWIM_WINDOW_T *win,
                        const COLOR_T *image,
                        INT_32 xsize,
                        INT_32 ysize,
                        INT_32 scale,
                        SWIM_ROTATION_T rtype);

 

Sorry, there is no specific code in the LPC18xx PDL. However, a SPI driver example is there as a starting point.

SWIM is a "Simple Windows Interface Manager". It basically provides non-overlapping window regions with simple graphics primitives and text operations. It's easy to use, a great learning tool, and it's free.

You can run up to 1024x768 at 24bpp as long as the bandwidth can be maintained by the LPC1788 and the DMA doesn't underflow. Unless you're driving that display size at a very low refresh rate, that specific configuration may not be feasible, as the bandwidth requirements will be higher than the LCP1788 can maintain. We offer a bandwidth calculator to help figure out if a specific configuration will be viable.

There are eight breakpoints. Six instruction breakpoints can be used to remap instruction addresses for code patches. Two data comparators can be used to remap addresses for patches to literal values.
There are four data watchpoints that can also be used as trace triggers. Additional information can be found in device User's Manuals.

Code Read Protection allows users to enable different levels of security in the system so they can protect both their software code and hardware.
There are several methods to program or read the Flash Memory:
- JTAG interface
- ISP (In-System Programming)
- IAP (In Application Programming)
The CRP Security levels limit the access in the following ways:
CRP1 (Level 1): Flash content can't be read. Full flash erase is possible. Flash updates (No Sector 0) using ISP.
CRP2 (Level 2): Flash content can't be read. Only Erase All using ISP.
CRP3 (Level 3): No ISP access. Even NXP can't access the code a CRP3 level. IAP reprogramming is possible. See AN10851 for details: http://www.lpcware.com/content/nxpfile/an10851-crp-example-source-code

The following formula may be used to calculate a parallel resonant crystal's external load capacitors:
CL = ((CX1 x CX2) / (CX1 + CX2)) + Cstray
where:
CL = the crystal load capacitance
Cstray = the stray capacitance in the oscillator circuit, which will normally be in the 2pF to 5pF range.

Assuming that CX1=CX2 then the equation becomes:
CL = ((CX1 x CX1) / (2 x CX1)) + Cstray
CL = (CX1 / 2) + Cstray
Rearranging the equation, we can find the external load capacitor value:
CX1 = 2(CL - Cstray)

For example, if the crystal load capacitance is 15pF, and assuming Cstray=2pF, then:
CX1 = CX2 = 2(15pF - 2pF) = 26pF

It is difficult to know exactly what the stray capacitance is, but if you find the oscillation frequency is too high, the load capacitor values can be increased. If the frequency is too low, the load capacitors can be decreased.
The device data sheet may also define a maximum crystal series resistance Rs.

Yes. In case of a software reset like WD reset, BOD reset etc, the SRAM contents (memory address 0x1000 0000 to 0x1000 2000 in case of LPC1227 ) is retained. However, the part won't retain the contents if it goes to deep power-down mode or if the microcontrollers is unpowered.

The LPCXpresso forum is a great place to start. The forum is found at http://knowledgebase.nxp.com/lpcxpresso.php
You can also find code examples at http://ics.nxp.com/support/lpcxpresso/

The LPCXpresso IDE is available for Windows, Linux and Mac OS X hosts. LPCXpresso can be downloaded from http://lpcxpresso.code-red-tech.com/LPCXpresso/.

The following formula may be used to calculate a parallel resonant crystal's external load capacitors:
CL = ((CX1 x CX2) / (CX1 + CX2)) + Cstray
where:
CL = the crystal load capacitance
Cstray = the stray capacitance in the oscillator circuit, which will normally be in the 2pF to 5pF range.

Assuming that CX1=CX2 then the equation becomes:
CL = ((CX1 x CX1) / (2 x CX1)) + Cstray
CL = (CX1 / 2) + Cstray
Rearranging the equation, we can find the external load capacitor value:
CX1 = 2(CL - Cstray)

For example, if the crystal load capacitance is 15pF, and assuming Cstray=2pF, then:
CX1 = CX2 = 2(15pF - 2pF) = 26pF

It is difficult to know exactly what the stray capacitance is, but if you find the oscillation frequency is too high, the load capacitor values can be increased. If the frequency is too low, the load capacitors can be decreased.
The device data sheet may also define a maximum crystal series resistance Rs.

Yes. In case of a software reset like WD reset, BOD reset etc, the SRAM contents (memory address 0x1000 0000 to 0x1000 2000 in case of LPC1227 ) is retained. However, the part won't retain the contents if it goes to deep power-down mode or if the microcontrollers is unpowered.

The IO pin will be 5V tolerant if the supply voltage Vdd is present, and they are configured as inputs. VDDIO must be applied to the microcontroller when input voltage is 5V, or else the 5V tolerance does not apply.

The LPCXpresso forum is a great place to start. The forum is found at http://knowledgebase.nxp.com/lpcxpresso.php
You can also find code examples at http://ics.nxp.com/support/lpcxpresso/

The LPCXpresso IDE is available for Windows, Linux and Mac OS X hosts. LPCXpresso can be downloaded from http://lpcxpresso.code-red-tech.com/LPCXpresso/.

The following formula may be used to calculate a parallel resonant crystal's external load capacitors:
CL = ((CX1 x CX2) / (CX1 + CX2)) + Cstray
where:
CL = the crystal load capacitance
Cstray = the stray capacitance in the oscillator circuit, which will normally be in the 2pF to 5pF range.

Assuming that CX1=CX2 then the equation becomes:
CL = ((CX1 x CX1) / (2 x CX1)) + Cstray
CL = (CX1 / 2) + Cstray
Rearranging the equation, we can find the external load capacitor value:
CX1 = 2(CL - Cstray)

For example, if the crystal load capacitance is 15pF, and assuming Cstray=2pF, then:
CX1 = CX2 = 2(15pF - 2pF) = 26pF

It is difficult to know exactly what the stray capacitance is, but if you find the oscillation frequency is too high, the load capacitor values can be increased. If the frequency is too low, the load capacitors can be decreased.
The device data sheet may also define a maximum crystal series resistance Rs.

Yes. In case of a software reset like WD reset, BOD reset etc, the SRAM contents (memory address 0x1000 0000 to 0x1000 2000 in case of LPC1227 ) is retained. However, the part won't retain the contents if it goes to deep power-down mode or if the microcontrollers is unpowered.

To place code in RAM, follow the link here:

http://support.code-red-tech.com/CodeRedWiki/CodeInRam

The IO pin will be 5V tolerant if the supply voltage Vdd is present, and they are configured as inputs. VDDIO must be applied to the microcontroller when input voltage is 5V, or else the 5V tolerance does not apply.

The LPCXpresso forum is a great place to start. The forum is found at http://knowledgebase.nxp.com/lpcxpresso.php
You can also find code examples at http://ics.nxp.com/support/lpcxpresso/

The LPCXpresso IDE is available for Windows, Linux and Mac OS X hosts. LPCXpresso can be downloaded from http://lpcxpresso.code-red-tech.com/LPCXpresso/.

The following formula may be used to calculate a parallel resonant crystal's external load capacitors:
CL = ((CX1 x CX2) / (CX1 + CX2)) + Cstray
where:
CL = the crystal load capacitance
Cstray = the stray capacitance in the oscillator circuit, which will normally be in the 2pF to 5pF range.

Assuming that CX1=CX2 then the equation becomes:
CL = ((CX1 x CX1) / (2 x CX1)) + Cstray
CL = (CX1 / 2) + Cstray
Rearranging the equation, we can find the external load capacitor value:
CX1 = 2(CL - Cstray)

For example, if the crystal load capacitance is 15pF, and assuming Cstray=2pF, then:
CX1 = CX2 = 2(15pF - 2pF) = 26pF

It is difficult to know exactly what the stray capacitance is, but if you find the oscillation frequency is too high, the load capacitor values can be increased. If the frequency is too low, the load capacitors can be decreased.
The device data sheet may also define a maximum crystal series resistance Rs.

Yes. In case of a software reset like WD reset, BOD reset etc, the SRAM contents (memory address 0x1000 0000 to 0x1000 2000 in case of LPC1227 ) is retained. However, the part won't retain the contents if it goes to deep power-down mode or if the microcontrollers is unpowered.

To place code in RAM, follow the link here:

http://support.code-red-tech.com/CodeRedWiki/CodeInRam

The IO pin will be 5V tolerant if the supply voltage Vdd is present, and they are configured as inputs. VDDIO must be applied to the microcontroller when input voltage is 5V, or else the 5V tolerance does not apply.

The LPCXpresso forum is a great place to start. The forum is found at http://knowledgebase.nxp.com/lpcxpresso.php
You can also find code examples at http://ics.nxp.com/support/lpcxpresso/

The LPCXpresso IDE is available for Windows, Linux and Mac OS X hosts. LPCXpresso can be downloaded from http://lpcxpresso.code-red-tech.com/LPCXpresso/.

The following formula may be used to calculate a parallel resonant crystal's external load capacitors:
CL = ((CX1 x CX2) / (CX1 + CX2)) + Cstray
where:
CL = the crystal load capacitance
Cstray = the stray capacitance in the oscillator circuit, which will normally be in the 2pF to 5pF range.

Assuming that CX1=CX2 then the equation becomes:
CL = ((CX1 x CX1) / (2 x CX1)) + Cstray
CL = (CX1 / 2) + Cstray
Rearranging the equation, we can find the external load capacitor value:
CX1 = 2(CL - Cstray)

For example, if the crystal load capacitance is 15pF, and assuming Cstray=2pF, then:
CX1 = CX2 = 2(15pF - 2pF) = 26pF

It is difficult to know exactly what the stray capacitance is, but if you find the oscillation frequency is too high, the load capacitor values can be increased. If the frequency is too low, the load capacitors can be decreased.
The device data sheet may also define a maximum crystal series resistance Rs.

Yes. In case of a software reset like WD reset, BOD reset etc, the SRAM contents (memory address 0x1000 0000 to 0x1000 2000 in case of LPC1227 ) is retained. However, the part won't retain the contents if it goes to deep power-down mode or if the microcontrollers is unpowered.

To place code in RAM, follow the link here:

http://support.code-red-tech.com/CodeRedWiki/CodeInRam

The IO pin will be 5V tolerant if the supply voltage Vdd is present, and they are configured as inputs. VDDIO must be applied to the microcontroller when input voltage is 5V, or else the 5V tolerance does not apply.

The LPCXpresso forum is a great place to start. The forum is found at http://knowledgebase.nxp.com/lpcxpresso.php
You can also find code examples at http://ics.nxp.com/support/lpcxpresso/

The LPCXpresso IDE is available for Windows, Linux and Mac OS X hosts. LPCXpresso can be downloaded from http://lpcxpresso.code-red-tech.com/LPCXpresso/.

The following formula may be used to calculate a parallel resonant crystal's external load capacitors:
CL = ((CX1 x CX2) / (CX1 + CX2)) + Cstray
where:
CL = the crystal load capacitance
Cstray = the stray capacitance in the oscillator circuit, which will normally be in the 2pF to 5pF range.

Assuming that CX1=CX2 then the equation becomes:
CL = ((CX1 x CX1) / (2 x CX1)) + Cstray
CL = (CX1 / 2) + Cstray
Rearranging the equation, we can find the external load capacitor value:
CX1 = 2(CL - Cstray)

For example, if the crystal load capacitance is 15pF, and assuming Cstray=2pF, then:
CX1 = CX2 = 2(15pF - 2pF) = 26pF

It is difficult to know exactly what the stray capacitance is, but if you find the oscillation frequency is too high, the load capacitor values can be increased. If the frequency is too low, the load capacitors can be decreased.
The device data sheet may also define a maximum crystal series resistance Rs.

Yes. In case of a software reset like WD reset, BOD reset etc, the SRAM contents (memory address 0x1000 0000 to 0x1000 2000 in case of LPC1227 ) is retained. However, the part won't retain the contents if it goes to deep power-down mode or if the microcontrollers is unpowered.

On the MCU, please check if the ISP pin is activated (ie. pulled LOW). Otherwise, every time the JTAG / SWD is reset, the MCU will go into bootROM, instead of the user program.

If the ISP pin is not pulled LOW, please check the IDE's configuration. For Keil, the 'Connect' option in Project ->Options for xxx ->Debug->Settings must be set to 'with pre-reset'. For IAR, set Project->Options->Debugger->"JTAG Name"->Reset to "Normal". If your project is using an external JTAG configuration (*.ini in Keil and *.mac in IAR), please make sure that it is configured to point to internal Flash or SRAM.

I2C0 pins are open-drain so they require external pull-ups.

I2C1 and I2C2 pins are not open-drain pins. The internal pull-ups could be enabled to pull the signals high when they are not driven low, but these pull-ups are weak compared to external pull-ups and are not recommended.

To place code in RAM, follow the link here:

http://support.code-red-tech.com/CodeRedWiki/CodeInRam

The IO pin will be 5V tolerant if the supply voltage Vdd is present, and they are configured as inputs. VDDIO must be applied to the microcontroller when input voltage is 5V, or else the 5V tolerance does not apply.

The LPCXpresso forum is a great place to start. The forum is found at http://knowledgebase.nxp.com/lpcxpresso.php
You can also find code examples at http://ics.nxp.com/support/lpcxpresso/

The LPCXpresso IDE is available for Windows, Linux and Mac OS X hosts. LPCXpresso can be downloaded from http://lpcxpresso.code-red-tech.com/LPCXpresso/.

The following formula may be used to calculate a parallel resonant crystal's external load capacitors:
CL = ((CX1 x CX2) / (CX1 + CX2)) + Cstray
where:
CL = the crystal load capacitance
Cstray = the stray capacitance in the oscillator circuit, which will normally be in the 2pF to 5pF range.

Assuming that CX1=CX2 then the equation becomes:
CL = ((CX1 x CX1) / (2 x CX1)) + Cstray
CL = (CX1 / 2) + Cstray
Rearranging the equation, we can find the external load capacitor value:
CX1 = 2(CL - Cstray)

For example, if the crystal load capacitance is 15pF, and assuming Cstray=2pF, then:
CX1 = CX2 = 2(15pF - 2pF) = 26pF

It is difficult to know exactly what the stray capacitance is, but if you find the oscillation frequency is too high, the load capacitor values can be increased. If the frequency is too low, the load capacitors can be decreased.
The device data sheet may also define a maximum crystal series resistance Rs.

Yes. In case of a software reset like WD reset, BOD reset etc, the SRAM contents (memory address 0x1000 0000 to 0x1000 2000 in case of LPC1227 ) is retained. However, the part won't retain the contents if it goes to deep power-down mode or if the microcontrollers is unpowered.

On the MCU, please check if the ISP pin is activated (ie. pulled LOW). Otherwise, every time the JTAG / SWD is reset, the MCU will go into bootROM, instead of the user program.

If the ISP pin is not pulled LOW, please check the IDE's configuration. For Keil, the 'Connect' option in Project ->Options for xxx ->Debug->Settings must be set to 'with pre-reset'. For IAR, set Project->Options->Debugger->"JTAG Name"->Reset to "Normal". If your project is using an external JTAG configuration (*.ini in Keil and *.mac in IAR), please make sure that it is configured to point to internal Flash or SRAM.

I2C0 pins are open-drain so they require external pull-ups.

I2C1 and I2C2 pins are not open-drain pins. The internal pull-ups could be enabled to pull the signals high when they are not driven low, but these pull-ups are weak compared to external pull-ups and are not recommended.

To place code in RAM, follow the link here:

http://support.code-red-tech.com/CodeRedWiki/CodeInRam

The IO pin will be 5V tolerant if the supply voltage Vdd is present, and they are configured as inputs. VDDIO must be applied to the microcontroller when input voltage is 5V, or else the 5V tolerance does not apply.

The LPCXpresso forum is a great place to start. The forum is found at http://knowledgebase.nxp.com/lpcxpresso.php
You can also find code examples at http://ics.nxp.com/support/lpcxpresso/

The LPCXpresso IDE is available for Windows, Linux and Mac OS X hosts. LPCXpresso can be downloaded from http://lpcxpresso.code-red-tech.com/LPCXpresso/.

The following formula may be used to calculate a parallel resonant crystal's external load capacitors:
CL = ((CX1 x CX2) / (CX1 + CX2)) + Cstray
where:
CL = the crystal load capacitance
Cstray = the stray capacitance in the oscillator circuit, which will normally be in the 2pF to 5pF range.

Assuming that CX1=CX2 then the equation becomes:
CL = ((CX1 x CX1) / (2 x CX1)) + Cstray
CL = (CX1 / 2) + Cstray
Rearranging the equation, we can find the external load capacitor value:
CX1 = 2(CL - Cstray)

For example, if the crystal load capacitance is 15pF, and assuming Cstray=2pF, then:
CX1 = CX2 = 2(15pF - 2pF) = 26pF

It is difficult to know exactly what the stray capacitance is, but if you find the oscillation frequency is too high, the load capacitor values can be increased. If the frequency is too low, the load capacitors can be decreased.
The device data sheet may also define a maximum crystal series resistance Rs.

Yes. In case of a software reset like WD reset, BOD reset etc, the SRAM contents (memory address 0x1000 0000 to 0x1000 2000 in case of LPC1227 ) is retained. However, the part won't retain the contents if it goes to deep power-down mode or if the microcontrollers is unpowered.

To place code in RAM, follow the link here:

http://support.code-red-tech.com/CodeRedWiki/CodeInRam

The IO pin will be 5V tolerant if the supply voltage Vdd is present, and they are configured as inputs. VDDIO must be applied to the microcontroller when input voltage is 5V, or else the 5V tolerance does not apply.

The LPCXpresso forum is a great place to start. The forum is found at http://knowledgebase.nxp.com/lpcxpresso.php
You can also find code examples at http://ics.nxp.com/support/lpcxpresso/

The LPCXpresso IDE is available for Windows, Linux and Mac OS X hosts. LPCXpresso can be downloaded from http://lpcxpresso.code-red-tech.com/LPCXpresso/.

The following formula may be used to calculate a parallel resonant crystal's external load capacitors:
CL = ((CX1 x CX2) / (CX1 + CX2)) + Cstray
where:
CL = the crystal load capacitance
Cstray = the stray capacitance in the oscillator circuit, which will normally be in the 2pF to 5pF range.

Assuming that CX1=CX2 then the equation becomes:
CL = ((CX1 x CX1) / (2 x CX1)) + Cstray
CL = (CX1 / 2) + Cstray
Rearranging the equation, we can find the external load capacitor value:
CX1 = 2(CL - Cstray)

For example, if the crystal load capacitance is 15pF, and assuming Cstray=2pF, then:
CX1 = CX2 = 2(15pF - 2pF) = 26pF

It is difficult to know exactly what the stray capacitance is, but if you find the oscillation frequency is too high, the load capacitor values can be increased. If the frequency is too low, the load capacitors can be decreased.
The device data sheet may also define a maximum crystal series resistance Rs.

Yes. In case of a software reset like WD reset, BOD reset etc, the SRAM contents (memory address 0x1000 0000 to 0x1000 2000 in case of LPC1227 ) is retained. However, the part won't retain the contents if it goes to deep power-down mode or if the microcontrollers is unpowered.

On the MCU, please check if the ISP pin is activated (ie. pulled LOW). Otherwise, every time the JTAG / SWD is reset, the MCU will go into bootROM, instead of the user program.

If the ISP pin is not pulled LOW, please check the IDE's configuration. For Keil, the 'Connect' option in Project ->Options for xxx ->Debug->Settings must be set to 'with pre-reset'. For IAR, set Project->Options->Debugger->"JTAG Name"->Reset to "Normal". If your project is using an external JTAG configuration (*.ini in Keil and *.mac in IAR), please make sure that it is configured to point to internal Flash or SRAM.

To place code in RAM, follow the link here:

http://support.code-red-tech.com/CodeRedWiki/CodeInRam

The IO pin will be 5V tolerant if the supply voltage Vdd is present, and they are configured as inputs. VDDIO must be applied to the microcontroller when input voltage is 5V, or else the 5V tolerance does not apply.

The LPCXpresso forum is a great place to start. The forum is found at http://knowledgebase.nxp.com/lpcxpresso.php
You can also find code examples at http://ics.nxp.com/support/lpcxpresso/

The LPCXpresso IDE is available for Windows, Linux and Mac OS X hosts. LPCXpresso can be downloaded from http://lpcxpresso.code-red-tech.com/LPCXpresso/.

The tiny FAT file system emulation in the bootloader uses a fixed translation from FAT cluster number to flash address. Once the old firmware has been deleted in the file browser (e.g Windows Explorer) on the host, all clusters are available for following write operations. Windows use them sequentially starting at the first available cluster. However, Linux starts at the second cluster, and this leads to the code ending up at the wrong location (here: 1 KB shifted, since a cluster contains two file system sectors of 512 bytes).

Both Windows and Linux do it perfectly right, because they can use clusters in any sequence they like. However, since the bootloader is translating the cluster no directly into Flash sector no, it may not working with different OS, other than Windows.

The following formula may be used to calculate a parallel resonant crystal's external load capacitors:
CL = ((CX1 x CX2) / (CX1 + CX2)) + Cstray
where:
CL = the crystal load capacitance
Cstray = the stray capacitance in the oscillator circuit, which will normally be in the 2pF to 5pF range.

Assuming that CX1=CX2 then the equation becomes:
CL = ((CX1 x CX1) / (2 x CX1)) + Cstray
CL = (CX1 / 2) + Cstray
Rearranging the equation, we can find the external load capacitor value:
CX1 = 2(CL - Cstray)

For example, if the crystal load capacitance is 15pF, and assuming Cstray=2pF, then:
CX1 = CX2 = 2(15pF - 2pF) = 26pF

It is difficult to know exactly what the stray capacitance is, but if you find the oscillation frequency is too high, the load capacitor values can be increased. If the frequency is too low, the load capacitors can be decreased.
The device data sheet may also define a maximum crystal series resistance Rs.

At this time, the LPC17xx and LPC18xx family of microcontrollers do not have a USB flash loader.

Yes. In case of a software reset like WD reset, BOD reset etc, the SRAM contents (memory address 0x1000 0000 to 0x1000 2000 in case of LPC1227 ) is retained. However, the part won't retain the contents if it goes to deep power-down mode or if the microcontrollers is unpowered.

NXP currently does not have a G.729 codec implemented for the NXP Cortex-M3 microcontrollers.

Yes, you can download AN10913: DSP library for LPC1300, LPC1700 and LPC1800 from http://www.lpcware.com/content/nxpfile/an10913-dsp-library-lpc1700-and-l...

On the MCU, please check if the ISP pin is activated (ie. pulled LOW). Otherwise, every time the JTAG / SWD is reset, the MCU will go into bootROM, instead of the user program.

If the ISP pin is not pulled LOW, please check the IDE's configuration. For Keil, the 'Connect' option in Project ->Options for xxx ->Debug->Settings must be set to 'with pre-reset'. For IAR, set Project->Options->Debugger->"JTAG Name"->Reset to "Normal". If your project is using an external JTAG configuration (*.ini in Keil and *.mac in IAR), please make sure that it is configured to point to internal Flash or SRAM.

To place code in RAM, follow the link here:

http://support.code-red-tech.com/CodeRedWiki/CodeInRam

The IO pin will be 5V tolerant if the supply voltage Vdd is present, and they are configured as inputs. VDDIO must be applied to the microcontroller when input voltage is 5V, or else the 5V tolerance does not apply.

The LPC13xx and LPC17xx families have a single ADC and sample-and-hold, so sampling multiple signals at the same time is not possible, unless an external sample-and-hold circuit is utilized.
The LPC18xx microcontrollers are a high performance Cortex-M3 family that has two ADCs, so it would be possible to sample multiple signals at the same time with these devices. The LPC43xx Cortex-M4 devices would also be an option since they also contain multiple ADCs.

The LPCXpresso forum is a great place to start. The forum is found at http://knowledgebase.nxp.com/lpcxpresso.php
You can also find code examples at http://ics.nxp.com/support/lpcxpresso/

The LPCXpresso IDE is available for Windows, Linux and Mac OS X hosts. LPCXpresso can be downloaded from http://lpcxpresso.code-red-tech.com/LPCXpresso/.

There are eight breakpoints. Six instruction breakpoints can be used to remap instruction addresses for code patches. Two data comparators can be used to remap addresses for patches to literal values.
There are four data watchpoints that can also be used as trace triggers. Additional information can be found in device User's Manuals.

The tiny FAT file system emulation in the bootloader uses a fixed translation from FAT cluster number to flash address. Once the old firmware has been deleted in the file browser (e.g Windows Explorer) on the host, all clusters are available for following write operations. Windows use them sequentially starting at the first available cluster. However, Linux starts at the second cluster, and this leads to the code ending up at the wrong location (here: 1 KB shifted, since a cluster contains two file system sectors of 512 bytes).

Both Windows and Linux do it perfectly right, because they can use clusters in any sequence they like. However, since the bootloader is translating the cluster no directly into Flash sector no, it may not working with different OS, other than Windows.

The following formula may be used to calculate a parallel resonant crystal's external load capacitors:
CL = ((CX1 x CX2) / (CX1 + CX2)) + Cstray
where:
CL = the crystal load capacitance
Cstray = the stray capacitance in the oscillator circuit, which will normally be in the 2pF to 5pF range.

Assuming that CX1=CX2 then the equation becomes:
CL = ((CX1 x CX1) / (2 x CX1)) + Cstray
CL = (CX1 / 2) + Cstray
Rearranging the equation, we can find the external load capacitor value:
CX1 = 2(CL - Cstray)

For example, if the crystal load capacitance is 15pF, and assuming Cstray=2pF, then:
CX1 = CX2 = 2(15pF - 2pF) = 26pF

It is difficult to know exactly what the stray capacitance is, but if you find the oscillation frequency is too high, the load capacitor values can be increased. If the frequency is too low, the load capacitors can be decreased.
The device data sheet may also define a maximum crystal series resistance Rs.

The DMAReqSel register can be configured to trigger a request from either UART0 or MAT0.0 but not both simultaneously.

“AN10851 Using CRP with the LPC1700" has an IAP software example. You can download the application note from http://www.lpcware.com/content/nxpfile/an10851-crp-example-source-code

Reading part IDs are the recommended way of determining the MAC IDs on different parts.

At this time, the LPC17xx and LPC18xx family of microcontrollers do not have a USB flash loader.

When a Framing error occurs, there is no way to reset/restart the UART state machine. Ideally, the best way to act upon this situation would be cleaning the FIFO up, and wait until an idle line is detected. After this, reception would continue normally.

Yes. In case of a software reset like WD reset, BOD reset etc, the SRAM contents (memory address 0x1000 0000 to 0x1000 2000 in case of LPC1227 ) is retained. However, the part won't retain the contents if it goes to deep power-down mode or if the microcontrollers is unpowered.

NXP currently does not have a G.729 codec implemented for the NXP Cortex-M3 microcontrollers.

Yes, you can download AN10913: DSP library for LPC1300, LPC1700 and LPC1800 from http://www.lpcware.com/content/nxpfile/an10913-dsp-library-lpc1700-and-l...

On the MCU, please check if the ISP pin is activated (ie. pulled LOW). Otherwise, every time the JTAG / SWD is reset, the MCU will go into bootROM, instead of the user program.

If the ISP pin is not pulled LOW, please check the IDE's configuration. For Keil, the 'Connect' option in Project ->Options for xxx ->Debug->Settings must be set to 'with pre-reset'. For IAR, set Project->Options->Debugger->"JTAG Name"->Reset to "Normal". If your project is using an external JTAG configuration (*.ini in Keil and *.mac in IAR), please make sure that it is configured to point to internal Flash or SRAM.

The LSR register in UART can detect:
*) Overrun - Data is missing due to UART RX FIFO is full
*) Parity error
*) Framing error - Error if the stop bit is missing
*) Break Interrupt.- Data is 0x00 (including parity bit)

However, UART cannot recover the missing bits from faulty transfer.

Time stamp feature is not available in the LPC17xx CAN controllers

Time stamp feature is not available in the LPC17xx CAN controllers

The input impedance of Vref is around 7k Ohms, so this should be taken into consideration when using a voltage divider on this input.

Boundary scan is not implemented on 176x/175x, therefore, there is no BSDL file available.

To check the MCU pin connection of the board, it is recommended that the user create their own software, to read the input pins, and to write HIGH / LOW to the output pins. Then the data can be dumped into serial port (or any available output peripheral or stored in the internal SRAM then read by JTAG).

I2C0 pins are open-drain so they require external pull-ups.

I2C1 and I2C2 pins are not open-drain pins. The internal pull-ups could be enabled to pull the signals high when they are not driven low, but these pull-ups are weak compared to external pull-ups and are not recommended.

Yes, check application note AN10916: FAT library EFSL and FatFs port on NXP LPC1700:
http://www.lpcware.com/content/nxpfile/an10916-fat-library-efsl-and-fatf...

Yes, the RTC oscillator can be used as a clock source for PLL0, however, when using PLL0 to drive the USB controller, the RTC cannot be used as the clock source. The reason it cannot be used for driving the USB controller is that an FREF less than 100 kHz will need to be used, and this causes a high jitter, which can cause a problem for PLL0.

TC and MRn registers can be written at any time.

For sleep mode, you will see a difference in current when changing the frequency. The peripherals can be powered off for lower consumption. The peripheral power consumption data can be found in the device datasheets.
In deep sleep, power-down and deep power-down modes, the frequency don’t affect these modes since the clocks are shut-off in the LPC17xx.

You can use a value of 450 uA/MHz as a rough value. Refer to LPC1700 low power mode app note which provides some tips to reduce the current.

The values in the datasheet are typical BOD levels although there is some hysteresis (minimum 0.4V).

The standard CMSIS libraries contain an NVIC_SystemReset() function. This function has the same effect as a hardware pin reset.

Yes, it is possible.

The maximum frequency of the SPI/SSP pins is 50MHz. Higher frequencies will affect the signal integrity of output.

“AN11178: MP3 player solution on NXP LPC1700” available for download from:
http://www.lpcware.com/content/nxpfile/an11178-mp3-player-solution-nxp-l...

Yes, this is normal behavior.

This is the event that occurs on ENET_RX_ER pin (P1.14), so if the PHY for some reason drove this pin high, it should (eventually) show up as a high SymbolError bit, and on Receive Status Vector bit 19. It's an indicator that the whole frame is suspect, and should be discarded. Basically, the PHY is indicating that there is an error raising the ENET_RX_ER line, and the user must investigate why the PHY is asserting this line

There is no power supply on and off sequence requirement for the LPC1700.

Usually it’s recommended to power up the IO, and then the core.

VSS and VSSA should be tied to GND

In the datasheet, there is a footnote regarding the short circuit which must be followed. There is no restriction on the time. Short circuit is allowed as long as the current doesn't exceed the max current (see limiting value) allowed by the device

Refer to the AN10974 LPC176x/175x 12-bit ADC design guidelines: http://www.nxp.com/documents/application_note/AN10974.pdf

To place code in RAM, follow the link here:

http://support.code-red-tech.com/CodeRedWiki/CodeInRam

The IO pin will be 5V tolerant if the supply voltage Vdd is present, and they are configured as inputs. VDDIO must be applied to the microcontroller when input voltage is 5V, or else the 5V tolerance does not apply.

At Power On Reset (POR) the IRC is the default clock source. Before switching to the XTAL oscillator, your code should wait for the PLL to lock with the XTAL before switching from the IRC.

Using a timer, wait for a defined period of time and if the PLL does not lock with the XTAL as the input clock source, switch the PLL clock source to the IRC.

During application code execution the WDT can be use to recover the device if the XTAL fails, resetting the device.

The startup code should check if the reset was due to the WDT timeout and if the XTAL will not lock, revert to the IRC. The Reset Source Identification Register (RSID) in the LPC17xx identifies the source of the reset.

The open source .NET Micro Framework requires a device with at least 256kB of flash and 64kB of RAM. A device with an external memory bus for memory expansion is highly recommended.

Please visit http://www.netmf.com/ for details on the .NET

There are two evaluation boards that support .NET MF:

* Embedded Artists EA_LPC2478 (NXP LPC2478 processor)

* Phytec Rapid Development Kit PCM023 (NXP LPC2294 processor)

There are several ways to wake up the processor, such as:
NMI, External Interrupts EINT0 through EINT3, GPIO interrupts, the Ethernet WOL interrupt, BOD, RTC Alarm interrupt, a WD Timer timeout, a USB input pin transition, a CAN input pin transition, as long as the related interrupt is enabled.
A UART may be used to wake the device from sleep mode but not from deep sleep mode and power-down mode. The UART can be running in sleep mode and when it receives a signal, it can generate an interrupt and wake the processor up.
In sleep mode, any enabled interrupt can wake the device up.

The internal voltage regulator voltage will always regulate around 1.8V where the external input voltage can range from 2.4V to 3.6V over the temperature range of -40C to 85C.

The internal voltage regulator will convert the external 3.3V to 1.8V. The 1.8V regulator powers the core domain, PLL, main oscillator, IRC with low power consumption.
As a result, the device is single supply device since the IOs supply shares the same range as the regulator supply input.

The LPC13xx and LPC17xx families have a single ADC and sample-and-hold, so sampling multiple signals at the same time is not possible, unless an external sample-and-hold circuit is utilized.
The LPC18xx microcontrollers are a high performance Cortex-M3 family that has two ADCs, so it would be possible to sample multiple signals at the same time with these devices. The LPC43xx Cortex-M4 devices would also be an option since they also contain multiple ADCs.

The LPCXpresso forum is a great place to start. The forum is found at http://knowledgebase.nxp.com/lpcxpresso.php
You can also find code examples at http://ics.nxp.com/support/lpcxpresso/

The LPCXpresso IDE is available for Windows, Linux and Mac OS X hosts. LPCXpresso can be downloaded from http://lpcxpresso.code-red-tech.com/LPCXpresso/.

There are eight breakpoints. Six instruction breakpoints can be used to remap instruction addresses for code patches. Two data comparators can be used to remap addresses for patches to literal values.
There are four data watchpoints that can also be used as trace triggers. Additional information can be found in device User's Manuals.

For the LPC17xx when the RTC is not used, connect VBAT to VDD(REG)(3V3) and leave RTCX1 floating. You should always refer to the data sheet and User's Manual for confirmation.

You can still use IAP when CRP is enabled. See AN10851 Using Code Read Protection in LPC1700 for details:
http://www.lpcware.com/content/nxpfile/an10851-crp-example-source-code

The erase time is 100±5% ms. This is independent of processor clock speed. You can erase one sector in 100 ms, or you can erase multiple sectors in the same time. Hence, a complete chip erase can be done in 100ms.
Programming time is 1.0±5% ms per Flash page (256 bytes). The programming time is given for writing 256 bytes from RAM to the flash. Data must be written to the flash in blocks of 256 bytes.

You will find a secondary USB bootloader application note and example software at http://www.lpcware.com/content/nxpfile/an10866-lpc1700-secondary-usb-boo...

Code Read Protection allows users to enable different levels of security in the system so they can protect both their software code and hardware.
There are several methods to program or read the Flash Memory:
- JTAG interface
- ISP (In-System Programming)
- IAP (In Application Programming)
The CRP Security levels limit the access in the following ways:
CRP1 (Level 1): Flash content can't be read. Full flash erase is possible. Flash updates (No Sector 0) using ISP.
CRP2 (Level 2): Flash content can't be read. Only Erase All using ISP.
CRP3 (Level 3): No ISP access. Even NXP can't access the code a CRP3 level. IAP reprogramming is possible. See AN10851 for details: http://www.lpcware.com/content/nxpfile/an10851-crp-example-source-code

Early versions of the LPC1751 microcontrollers did not support CRP. These devices can be identified with Part ID 25001110 and with date codes prior to 1013. Newer LPC1751 devices with part ID 25001118 have the CRP feature implemented. An Errata sheet has been created in this regard. The errata sheet can be downloaded from http://www.lpcware.com/gfiles/devper/lpc175x_6x.

The Ethernet PHY configuration is a one-time event. Once the configuration has been completed using MDIO and MCLK, these pins will no longer be required. It will then be possible to switch the pin function to USB.
Another option is to use Ethernet MII Management (MDIO) using software. This is described in Application note AN10859.
http://www.lpcware.com/content/nxpfile/an10859-lpc1700-easyweb
If MDIO is implemented in software, there will be no need to share pins between USB and Ethernet.

SNR characterization has not been done for LPC1700 ADC.

Ethernet bootloaders are available as part of the Flash Magic tool ( www.flashmagictool.com). After installing Flash Magic, you can find the bootloader in the Flash Magic\Ethernet Bootloader directory (C:\Program Files (x86)\Flash Magic\Ethernet Bootloader in a Windows x64 environment). An application note is available for download from http://www.lpcware.com/content/nxpfile/an10744-ethernet-secondary-isp-bo...

Yes, NXP has developed an IEC60335 library that can be used with any of our Cortex-M3 based microcontrollers. Application note AN10918 has been written as a guide to use and implement the library. The application note can be downloaded from http://www.lpcware.com/content/nxpfile/an10918-nxp-lpc-cortex-m3-iec6033...

The tiny FAT file system emulation in the bootloader uses a fixed translation from FAT cluster number to flash address. Once the old firmware has been deleted in the file browser (e.g Windows Explorer) on the host, all clusters are available for following write operations. Windows use them sequentially starting at the first available cluster. However, Linux starts at the second cluster, and this leads to the code ending up at the wrong location (here: 1 KB shifted, since a cluster contains two file system sectors of 512 bytes).

Both Windows and Linux do it perfectly right, because they can use clusters in any sequence they like. However, since the bootloader is translating the cluster no directly into Flash sector no, it may not working with different OS, other than Windows.

The following formula may be used to calculate a parallel resonant crystal's external load capacitors:
CL = ((CX1 x CX2) / (CX1 + CX2)) + Cstray
where:
CL = the crystal load capacitance
Cstray = the stray capacitance in the oscillator circuit, which will normally be in the 2pF to 5pF range.

Assuming that CX1=CX2 then the equation becomes:
CL = ((CX1 x CX1) / (2 x CX1)) + Cstray
CL = (CX1 / 2) + Cstray
Rearranging the equation, we can find the external load capacitor value:
CX1 = 2(CL - Cstray)

For example, if the crystal load capacitance is 15pF, and assuming Cstray=2pF, then:
CX1 = CX2 = 2(15pF - 2pF) = 26pF

It is difficult to know exactly what the stray capacitance is, but if you find the oscillation frequency is too high, the load capacitor values can be increased. If the frequency is too low, the load capacitors can be decreased.
The device data sheet may also define a maximum crystal series resistance Rs.

The DMAReqSel register can be configured to trigger a request from either UART0 or MAT0.0 but not both simultaneously.

“AN10851 Using CRP with the LPC1700" has an IAP software example. You can download the application note from http://www.lpcware.com/content/nxpfile/an10851-crp-example-source-code

Reading part IDs are the recommended way of determining the MAC IDs on different parts.

At this time, the LPC17xx and LPC18xx family of microcontrollers do not have a USB flash loader.

When a Framing error occurs, there is no way to reset/restart the UART state machine. Ideally, the best way to act upon this situation would be cleaning the FIFO up, and wait until an idle line is detected. After this, reception would continue normally.

Yes. In case of a software reset like WD reset, BOD reset etc, the SRAM contents (memory address 0x1000 0000 to 0x1000 2000 in case of LPC1227 ) is retained. However, the part won't retain the contents if it goes to deep power-down mode or if the microcontrollers is unpowered.

NXP currently does not have a G.729 codec implemented for the NXP Cortex-M3 microcontrollers.

Yes, you can download AN10913: DSP library for LPC1300, LPC1700 and LPC1800 from http://www.lpcware.com/content/nxpfile/an10913-dsp-library-lpc1700-and-l...

On the MCU, please check if the ISP pin is activated (ie. pulled LOW). Otherwise, every time the JTAG / SWD is reset, the MCU will go into bootROM, instead of the user program.

If the ISP pin is not pulled LOW, please check the IDE's configuration. For Keil, the 'Connect' option in Project ->Options for xxx ->Debug->Settings must be set to 'with pre-reset'. For IAR, set Project->Options->Debugger->"JTAG Name"->Reset to "Normal". If your project is using an external JTAG configuration (*.ini in Keil and *.mac in IAR), please make sure that it is configured to point to internal Flash or SRAM.

The LSR register in UART can detect:
*) Overrun - Data is missing due to UART RX FIFO is full
*) Parity error
*) Framing error - Error if the stop bit is missing
*) Break Interrupt.- Data is 0x00 (including parity bit)

However, UART cannot recover the missing bits from faulty transfer.

Time stamp feature is not available in the LPC17xx CAN controllers

Time stamp feature is not available in the LPC17xx CAN controllers

The input impedance of Vref is around 7k Ohms, so this should be taken into consideration when using a voltage divider on this input.

I2C0 pins are open-drain so they require external pull-ups.

I2C1 and I2C2 pins are not open-drain pins. The internal pull-ups could be enabled to pull the signals high when they are not driven low, but these pull-ups are weak compared to external pull-ups and are not recommended.

Yes, check application note AN10916: FAT library EFSL and FatFs port on NXP LPC1700:
http://www.lpcware.com/content/nxpfile/an10916-fat-library-efsl-and-fatf...

Yes, this is normal behavior.

This is the event that occurs on ENET_RX_ER pin (P1.14), so if the PHY for some reason drove this pin high, it should (eventually) show up as a high SymbolError bit, and on Receive Status Vector bit 19. It's an indicator that the whole frame is suspect, and should be discarded. Basically, the PHY is indicating that there is an error raising the ENET_RX_ER line, and the user must investigate why the PHY is asserting this line

There is no power supply on and off sequence requirement for the LPC1700.

Usually it’s recommended to power up the IO, and then the core.

VSS and VSSA should be tied to GND

In the datasheet, there is a footnote regarding the short circuit which must be followed. There is no restriction on the time. Short circuit is allowed as long as the current doesn't exceed the max current (see limiting value) allowed by the device

Refer to the AN10974 LPC176x/175x 12-bit ADC design guidelines: http://www.nxp.com/documents/application_note/AN10974.pdf

To place code in RAM, follow the link here:

http://support.code-red-tech.com/CodeRedWiki/CodeInRam

The IO pin will be 5V tolerant if the supply voltage Vdd is present, and they are configured as inputs. VDDIO must be applied to the microcontroller when input voltage is 5V, or else the 5V tolerance does not apply.

At Power On Reset (POR) the IRC is the default clock source. Before switching to the XTAL oscillator, your code should wait for the PLL to lock with the XTAL before switching from the IRC.

Using a timer, wait for a defined period of time and if the PLL does not lock with the XTAL as the input clock source, switch the PLL clock source to the IRC.

During application code execution the WDT can be use to recover the device if the XTAL fails, resetting the device.

The startup code should check if the reset was due to the WDT timeout and if the XTAL will not lock, revert to the IRC. The Reset Source Identification Register (RSID) in the LPC17xx identifies the source of the reset.

The open source .NET Micro Framework requires a device with at least 256kB of flash and 64kB of RAM. A device with an external memory bus for memory expansion is highly recommended.

Please visit http://www.netmf.com/ for details on the .NET

There are two evaluation boards that support .NET MF:

* Embedded Artists EA_LPC2478 (NXP LPC2478 processor)

* Phytec Rapid Development Kit PCM023 (NXP LPC2294 processor)

There are several ways to wake up the processor, such as:
NMI, External Interrupts EINT0 through EINT3, GPIO interrupts, the Ethernet WOL interrupt, BOD, RTC Alarm interrupt, a WD Timer timeout, a USB input pin transition, a CAN input pin transition, as long as the related interrupt is enabled.
A UART may be used to wake the device from sleep mode but not from deep sleep mode and power-down mode. The UART can be running in sleep mode and when it receives a signal, it can generate an interrupt and wake the processor up.
In sleep mode, any enabled interrupt can wake the device up.

The internal voltage regulator voltage will always regulate around 1.8V where the external input voltage can range from 2.4V to 3.6V over the temperature range of -40C to 85C.

The internal voltage regulator will convert the external 3.3V to 1.8V. The 1.8V regulator powers the core domain, PLL, main oscillator, IRC with low power consumption.
As a result, the device is single supply device since the IOs supply shares the same range as the regulator supply input.

The LPC13xx and LPC17xx families have a single ADC and sample-and-hold, so sampling multiple signals at the same time is not possible, unless an external sample-and-hold circuit is utilized.
The LPC18xx microcontrollers are a high performance Cortex-M3 family that has two ADCs, so it would be possible to sample multiple signals at the same time with these devices. The LPC43xx Cortex-M4 devices would also be an option since they also contain multiple ADCs.

The LPCXpresso forum is a great place to start. The forum is found at http://knowledgebase.nxp.com/lpcxpresso.php
You can also find code examples at http://ics.nxp.com/support/lpcxpresso/

The LPCXpresso IDE is available for Windows, Linux and Mac OS X hosts. LPCXpresso can be downloaded from http://lpcxpresso.code-red-tech.com/LPCXpresso/.

There are eight breakpoints. Six instruction breakpoints can be used to remap instruction addresses for code patches. Two data comparators can be used to remap addresses for patches to literal values.
There are four data watchpoints that can also be used as trace triggers. Additional information can be found in device User's Manuals.

For the LPC17xx when the RTC is not used, connect VBAT to VDD(REG)(3V3) and leave RTCX1 floating. You should always refer to the data sheet and User's Manual for confirmation.

It looks like it's getting stuck on NAND detection. It's very possible that a jumper related to NAND ready/busy on that board may not be set correctly.

Yes, the 208 pin versions of the LPC178x are pin-compatible with the LPC2478 and LPC2470.

If it happens, a DMA underflow will occur causing a tear. For the frame being rendered when this happens, the data under the spot of the display where the tear happen will be misaligned. Because the frame is being updated at a high rate (60Hz?), you see a quick flicker on the display. If the tear happens a lot, the flicker can be annoying.
It should be noted that the LCD controller will underflow only when it's DMA request is stalled for a considerable amount of time. The LCD controller has it's own buffer memory filled up by DMA and can handle short stalls during it's DMA request.

Not necessarily, it really depends on the LCD resolution, clock rate, etc. Using a 16-bit interface will have more of a chance for tearing and won't be able to handle as big a display as a 32-bit interface.

The size limit for the LCD frame buffer is 1024x1024x4, which would be a 1k x 1k x 24bpp display. You can compute a frame buffers memory requirements by multiplying the X resolution by the Y resolution by the color depth in bytes. For example, a 320x240 display at 16bpp (2bytes per pixel) would need 320x240x2 = about 150kB. You can also use the bandwidth calculator to compute this value.

LPC247x bus bandwidth calculator:
http://www.lpcware.com/content/nxpfile/lpc247x-lcd-bus-load-calculator

LPC178x and LPC40xx bus bandwidth calculator:
http://www.lpcware.com/content/nxpfile/lcd-bus-bandwidth-calculator-lpc1...

LPC18xx and LPC43xx bus bandwidth calculator:
http://www.lpcware.com/content/nxpfile/lcd-bandwidth-calculator-lpc18xx-...

The signals are not LVDS. You'll need a converter if you are using a display with an LVDS interface.

The internal RAM is not dedicated for video memory. All memory - external or internal - can be shared with the LCD controller.

The LCD controller is it's own bus master and isn't part of the GP DMA module. DMA operation for the LCD controller is pretty much transparent - all you need to do is setup the LCD controller and point the frame buffer to an address.

The LCD DMA keeps the LCD FIFO full. It can only DMA from the LCD framebuffer which must be a contiguous block of memory. Scatter-gather support isn't provided, but due to the nature of how the frame buffer must be arranged (in physical memory), scatter-gather support isn't really needed.

If the LCD controller has higher priority than the other devices that use the EMC, the other devices will be delayed until they can get the EMC bus. In the case of the CPU, the CPU will stall until it can get the bus. Unless the DMA request rate is very high, the CPU stalls shouldn't impact performance too much.

The frame buffer can be in any contiguous block of memory. This could include a block of internal SRAM or in external SDRAM or SRAM. Usually, the frame buffer storage requirement (depends on LCD resolution and colors) is too large to fit in internal SRAM and external SDRAM is used.

You can run up to 1024x768 at 24bpp as long as the bandwidth can be maintained by the LPC1788 and the DMA doesn't underflow. Unless you're driving that display size at a very low refresh rate, that specific configuration may not be feasible, as the bandwidth requirements will be higher than the LCP1788 can maintain. We offer a bandwidth calculator to help figure out if a specific configuration will be viable.

The LPC1788 includes the same memory controller except for the addition an optional address shift mode for static memories that can simplify the board design and potentially increases external memory addressing range in some cases. The LPC1788 is pin-compatible with the LPC2478 but contains a Cortex M3 processor core instead of an ARM7.

The following formula may be used to calculate a parallel resonant crystal's external load capacitors:
CL = ((CX1 x CX2) / (CX1 + CX2)) + Cstray
where:
CL = the crystal load capacitance
Cstray = the stray capacitance in the oscillator circuit, which will normally be in the 2pF to 5pF range.

Assuming that CX1=CX2 then the equation becomes:
CL = ((CX1 x CX1) / (2 x CX1)) + Cstray
CL = (CX1 / 2) + Cstray
Rearranging the equation, we can find the external load capacitor value:
CX1 = 2(CL - Cstray)

For example, if the crystal load capacitance is 15pF, and assuming Cstray=2pF, then:
CX1 = CX2 = 2(15pF - 2pF) = 26pF

It is difficult to know exactly what the stray capacitance is, but if you find the oscillation frequency is too high, the load capacitor values can be increased. If the frequency is too low, the load capacitors can be decreased.
The device data sheet may also define a maximum crystal series resistance Rs.

At this time, the LPC17xx and LPC18xx family of microcontrollers do not have a USB flash loader.

Yes. In case of a software reset like WD reset, BOD reset etc, the SRAM contents (memory address 0x1000 0000 to 0x1000 2000 in case of LPC1227 ) is retained. However, the part won't retain the contents if it goes to deep power-down mode or if the microcontrollers is unpowered.

NXP currently does not have a G.729 codec implemented for the NXP Cortex-M3 microcontrollers.

Yes, you can download AN10913: DSP library for LPC1300, LPC1700 and LPC1800 from http://www.lpcware.com/content/nxpfile/an10913-dsp-library-lpc1700-and-l...

To place code in RAM, follow the link here:

http://support.code-red-tech.com/CodeRedWiki/CodeInRam

The IO pin will be 5V tolerant if the supply voltage Vdd is present, and they are configured as inputs. VDDIO must be applied to the microcontroller when input voltage is 5V, or else the 5V tolerance does not apply.

The LPC13xx and LPC17xx families have a single ADC and sample-and-hold, so sampling multiple signals at the same time is not possible, unless an external sample-and-hold circuit is utilized.
The LPC18xx microcontrollers are a high performance Cortex-M3 family that has two ADCs, so it would be possible to sample multiple signals at the same time with these devices. The LPC43xx Cortex-M4 devices would also be an option since they also contain multiple ADCs.

The LPCXpresso forum is a great place to start. The forum is found at http://knowledgebase.nxp.com/lpcxpresso.php
You can also find code examples at http://ics.nxp.com/support/lpcxpresso/

The LPCXpresso IDE is available for Windows, Linux and Mac OS X hosts. LPCXpresso can be downloaded from http://lpcxpresso.code-red-tech.com/LPCXpresso/.

There are eight breakpoints. Six instruction breakpoints can be used to remap instruction addresses for code patches. Two data comparators can be used to remap addresses for patches to literal values.
There are four data watchpoints that can also be used as trace triggers. Additional information can be found in device User's Manuals.

Sorry, there is no specific code in the LPC18xx PDL. However, a SPI driver example is there as a starting point.