I'm making SDRAM layout for LPC1788. I want to do it right so I make timing budget calculations based on this article:
I think there are some errors in current datasheet (rev. 4 - May 2012) of LPC1788 (Table 18 on page 25):
th(Q) data output hold time min. 0.2ns max 1.6ns
If I understand it correctly this means, that data output is valid only for 0.2ns (worst case) after clock. My memory device, has minimum input hold time 0.8ns (and as I know most SDRAM's has similar value). Output hold time can't be lower than input hold time. I think this th(Q) is much to low.
I compared it with LPC1850 datasheet and in my opinion this is correct value (Table 23 on page 115):
th(Q) data output hold time min. 0.5 × Tcy(clk) ns
where Tcy(clk) is clock period.
Also, I cant find any SDRAM layout guidelines for this microprocessor. I know there is Application Note for LPC32xx, but I can't find one for LPC1788.