Forum for lpc17xx devices

LPC1768FBD100 USB Host communicate with keyboards.

Attached please find the debug information. The followings are for summaries for your reference.

1. The viewer to open the USB log file.

2. If the sent data is more than one byte, there is no problem when re-sends the data.
3. The retry is done by the hardware, the software does nothing for it.
4. The phenomenon can be reproduced by the attached software and NXP ev board.

Help with can bus and VW car

Hello. Does anybody help me with this?....i wanna conect the lpcxpresso 1769 to my VW car and read the RPM values...Is this possible?...Is this very hard to do?...I wanna do this for my college project but i dont have idea about can

change PWM frequency

The code below sets up a simple 2-edged PWM signal. In my application, I need to change the frequency occasionally, which is what I THINK I am doing in the main loop, but the only change is the duty cycle. That is, the frequency always remains to what it was set at the beginning (1kHz), and only the "on" duty cycle is commensurate with the 2kHz I'm switching it to.

SPI Slave TX Underrun

I figured this has to be documented somewhere but i can't seem to find it. What exactly happens if i am running as an SPI Slave on the LPC1788 and my TX buffer is underrun?

By testing i think i have figured out what happens, but it is undesirable behavior.

What i am seeing in testing is this (SPI_MODE_1):

Master sends LPC a 5 Byte Message: t,e,s,t,Line Break
During this transmission the LPC slave sends 0's
Master then clocks out 10 lines for the LPC to respond.

Ethernet Programming -- Checksums

My project uses the EMAC block of the LPC1778 -- but presumably this peripheral is common to other NXP parts.

Because I reject any received frame with a CRC error (Ethernet level FCS), I do not bother to verify
the various checksums.

My reasoning is that if an error occured that might be detected by checksum verification, it would also
cause a CRC error at the frame level [and the CRC is much stronger than a mere checksum].

Does anyone care to comment on this strategy? Or provide a counter example.

Cheers, Mike

lpc1788, lpcopen, openocd and lpcopen-make

Im new to ARM programming, AVR 8 bit programming has been a hobby of mine for about 5 years, I have bought a development board from olimex however the example they have written is for IAR IDE and has lots of proprietry code in, and the IDE is like $2000 - I cant afford that, so I want to go open source.
This is the dev board I bought; https://www.olimex.com/Products/Modules/LCD/MOD-LCD4.3%27%27/
I have setup a ubuntu box with the above mentioned toolchain.

LPC1769 LWIP stack assert pbuf->ref=1 fail

I am running LWIP stack on LPC1769, compiler is IAR, source code is from LPCOpen 1.03 echo sample without RTOS. board is LPCXpresso board. I modified the sample to open 6 tcp server and 6 tcp client socket. the stack assert fail at pbuf->ref==1 (ip.c ln 865 ) after running a while. the timing is random, sometime after send/receive several thousand packet, sometime after several 10K packet. Is there anybody know the reason of it? attached is the opt.h and lwipopts.h Thanks.

Does anyone have u-boot running on the Future Designs LPC1788 board?

Hi there,

Has anyone tried porting u-boot to the FDI LPC1788 evaluation board?

I've tried working with the Emcraft version, but the SDRAM configuration is different (The EA1788 uses an ISSC part while the FDI is using a Micron part).

Getting the EMC configuration correct has been difficult. I'm hoping someone else out there has already tried this and has some tips.


CCLK and SDRAM DynamicRefresh


I am trying to reduce the CCLK in order to save power, but I am concerned that the SDRAM will suffer from this, as the EMC CLK is equal to CCLK.

Is it okay to change the Dynamic Refresh Register on the fly?

Basicly I am doing this:

if ( Mode == POWER_SAVE )
LPC_EMC->DynamicRefresh = 0x00000023; /* ( n * 16 ) -> 560 clock cycles -> 15.560uS at 48MHz <= 15.625uS ( 64ms / 4096 row ) */
LPC_SC->CCLKSEL = 0x104; // Set Clk to 36 MHz
LPC_SC->CCLKSEL = 0x102; // Set Clk to 48 MHz

LPC1788 - ENET_IRQHandler()


I'm using NXP's EMAC Driver lpc177x_8x_emac.c.
When a packet is received, in the ENET_IRQHandler() a callback function registred as Emac_ConfigStruct.pfnFrameReceive is called.

If I spend a longer time processing the packet in this function (and implicitly in the interrupt routine) and during this a second packet is received, it will not fire the interrupt again.