I have a custom designed board populated with the LPC1788 and a 32-bit wide SDRAM chip. I seem to be having bus contention issues between the LCD and my frame buffer update routine. I have found that if I allow them to access the memory space simultaneously the LCD gets out of sync and displays pseudo-random data. So if I load buffer #1 with half red data and the other half with blue, the LCD will display this beautifully. As soon as I begin accessing (asynchonrously) the SDRAM to write to buffer 2, the blue and red data start mixing randomly. Does anyone know how to synchronize my buffer updates with the LCD DMA requests so that I don't step on those requests? I thought changing the matrix arbitration register might help but that did not seem to make a difference which is also puzzling.
And on a related note, what was NXP thinking forcing users to under-clock the CPU if they want to use SDRAM?! Why is the EMC limited to 80MHz?
Thanks in advance for any advice given!