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FAQs found

Question Last updated
After a software reset like WD reset, BOD reset, is the SRAM content retained? 2012-12-04 12:13
Are the LCD controller signals LVDS? 2012-11-20 16:17
Are there any DSP libraries available for the Cortex-M3 microcontrollers ? 2012-11-27 00:30
Debugging LPC18xx/LPC43xx images built to run from internal RAM 2016-02-23 08:05
Do the LPC17xx and LPC18xx have USB Flash loader like the LPC1343? 2012-12-11 15:29
Do you have size limit or memory size calculator to help set the size of the frame buffer? 2012-11-20 16:28
How do I configure Lpcxpresso to place code in RAM? 2012-11-21 16:07
How many breakpoints and watchpoints are supported on LPC17xx and other Cortex-M3 devices? 2012-11-19 13:24
How to calculate the value of crystal load capacitors? 2012-12-21 14:25
How to use touchscreen support of LCD Logicpd 4.3'' WQVGA and LPC1850? 2012-11-20 15:24
If the LCD controller has a lower priority on the EMC bus, refreshes will be stalled. How noticable is this on the screen? 2012-11-20 16:33
Is it possible to sample two analog signals at the same time on a Cortex-M3 device? 2012-11-19 13:30
Is the LCD DMA a gather scatter DMA ? Where is it located exactly ? 2012-11-20 16:39
Is the LCD DMA located in the LCD macrocell or the GP DMA ? 2012-11-20 16:40
Is there any G.729 codec implemented for any Cortex-M3 cores? 2012-11-27 00:32
Is there dedicated on-board SRAM memory specifically for the frame buffer? 2012-11-20 16:42
The datasheet mentions the I/O pins are 5V tolerant if Vdd is present. Can you explain in detail what this implies? 2012-11-21 16:03
What platforms are supported by LPCXpresso? 2012-11-19 13:26
Where should I go for LPCXpresso related support? 2012-11-19 13:28
Which Cortex-M CPU revision is implemented in NXP microcontrollers? 2013-12-27 14:26
Will using a 16-bit external bus be too slow for LCD, causing tearing to occur? 2012-11-20 16:46